Multiple voted logic cell testable by a scan chain and system and method of testing the same
AssigneeGoodrich Corporation
InventorsArthur Howard Waldie, Robert Ward James, Kuo-Chuan Chang
Life of this patent
Estimating the term…
Abstract
A multiple voted integrated circuit logic cell testable by a scan chain comprises: an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of the registers for generating an output signal of the logic cell; and a circuit coupled to each latching register for altering selectively the scan chain data signal input thereto. A scan chain test system for and method of testing at least one multiple voted logic cell of the aforementioned type are also disclosed.
Claims26
A multiple voted integrated circuit logic cell testable by a test data signed to determine whether or not the cell is faulty, said cell comprising:
- odd plurality of latching registers, each register having a data input for receiving said test data signal and capable of latching said test data signal and generating an output signal representative thereof;
- multiple vote circuit governed by the output signals of said registers for generating an output signal of said logic cell;
- and
- circuit means coupled to each said register for altering selectively the test data signal input thereto.
A scan chain test system for testing at least one multiple voted logic cell of an integrated circuit including a scan chain, said system comprising:
- at least one integrated circuit logic cell, coupled to said scan chain, comprising:
- an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal from said scan chain and capable of latching said scan chain data signal and generating an output signal representative thereof;
- a multiple vote circuit governed by the output signals of said registers for generating an output signal of said logic cell over said scan chain;
- and
- circuit means coupled to each said register for altering selectively the scan chain data signal input thereto;
- and
- a scan chain test controller operable to apply the scan chain data signal to said at least one logic cell of said integrated circuit and control the value thereof, said controller further operable to control the circuit means for altering selectively the scan chain data signal input to each latching register and for receiving and analyzing the logic cell output signals from said at least one logic cell in response to the applied scan chain data signal and the controlled selective alterations thereof to determine a fault in said at least one logic cell.
Method of testing at least one multiple voted logic cell of an integrated circuit, each multiple voted logic cell comprising:
- an odd plurality of latching registers, each register having a data input for receiving a test data signal and capable of latching said test data signal and generating an output signal representative thereof;
- and a multiple vote circuit governed by the output signals of said registers for generating an output signal of said logic cell, said method comprising the steps of:
- applying the test data signal to the data input of each of the latching registers of at least one multiple voted logic cell of said integrated circuit;
- controlling the value of the applied test data signal;
- altering selectively the test data signal input to each latching register;
- and
- receiving and analyzing the logic cell output signals from said at least one logic cell in response to the applied test data signal and the selective alterations thereof to determine a fault in said at least one logic cell.
Dependencies are inferred from the claim text.