Charge gain stress test circuit for nonvolatile memory and test method using the same

#1. Field of the Invention

#The present invention relates to a memory device, and more particularly, a charge gain stress test (CGST) circuit for a memory device and a test method using the same.

#2. Background of the Related Art

#The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:

#FIG. 1 is a circuit diagram of a CGST circuit of a flash memory in the background art;

#FIG. 2 is a graph illustrating a characteristic of a flash memory cell of the CGST circuit illustrated in FIG. 1;

#FIG. 3 illustrates a CGST circuit of a flash memory according to a preferred embodiment of the present invention. A reference current generating unit 10 generates a reference current Iref, and a sense amp 20 outputs a compare result SOUT by comparing the reference current Iref with a cell current Icell. A first switch SW11 is controlled by a first control signal READ to connect the sense amp 20 or a ground source voltage VSS to a drain of the flash memory cell 30. A second switch SW12 is controlled by the first control signal READ for selectively connecting the ground source voltage VSS or a stress voltage Vpps to a gate of the flash memory cell 30, or is controlled by a second control signal ERASE for thereby controlling the ground source voltage VSS or a first erase voltage to the gate of the flash memory cell 30. A third switch SW13 is controlled by the second control signal ERASE for selectively connecting the ground source voltage VSS or a second erase voltage Ver to a source of the flash memory cell 30.

#The first erase voltage Vppe is the ground source voltage VSS or a negative voltage. The second erase voltage Ver has a positive voltage when the first erase voltage Vppe is a ground source voltage VSS, and has a ground source voltage VSS or positive voltage when the first erase voltage Vppe is a negative voltage.

#In such a CGST circuit, the first switch SW11 connects the drain of the flash memory cell 30 with the sense amp 20 in accordance with the first control signal READ. The second switch SW12 connects the gate of the flash memory cell 30 with the ground source voltage VSS in accordance with the first and second control signals READ and ERASE. The third switch SW13 connects the source of the flash memory 30 to the ground source voltage VSS in accordance with the second control signal ERASE.