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US 6,480,017 B2Granted
Evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing
AssigneeOki Electric Industry Co., Ltd.
InventorTadashi Narita
Life of this patent
Estimating the term…
Abstract
An evaluating pattern includes conductive pattern which has a rectangular configuration, an insulating layer which is formed on the conductive pattern, and a conductive material filled into contact holes which is formed in the insulating layer on the middle of the conductive pattern.
Claims15
An evaluating pattern for measuring erosion of a semiconductor wafer which is polished by chemical mechanical polishing, comprising:
- a conductive pattern which has a rectangular configuration;
- an insulating layer which is formed on the conductive pattern;
- contact holes formed through the insulating layer to the conductive pattern;
- and
- a conductive material filled into the contact holes.
2 more elements
An evaluating pattern for measuring erosion of a semiconductor wafer which is polished by chemical mechanical polishing, comprising:
- a rectangular conductive pattern which has a middle region, a first region which surrounds the middle region and a second region which surrounds the first region;
- an insulating layer which is formed on the first, second and middle regions of the rectangular conductive pattern;
- contact holes formed through the insulating layer to the first region of the rectangular conductive pattern;
- and
- a conductive material filled into the contact holes.
2 more elements
Dependencies are inferred from the claim text.