Semiconductor device testing apparatus having timing hold function

Abstract

There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories. At the start of the testing apparatus, the signal propagation delay times of the test pattern supply path and the strobe pulse supply path are adjusted on the basis of the respective delay correcting data stored in the non-volatile memory or memories, respectively.

Dependencies are inferred from the claim text.