MOS current sense circuit

A current sense circuit comprising:

• a first MOS transistor having a gate, a drain, and a source wherein said gate is coupled to a control signal, wherein said drain is coupled to a load such that a load current flows through said first MOS transistor when said control signal is ON, and wherein said first MOS transistor has a first width-to-length ratio;
• a second MOS transistor having a gate, a drain, and a source wherein said gate is coupled to said control signal,
• wherein said drain is coupled to a constant current source such that said constant current flows through said second MOS transistor when said control signal is ON, wherein said source is coupled to said source of said first MOS transistor, wherein said first and second MOS transistors are operating in the linear region when said control signal is ON, wherein said second MOS transistor has a second width-to-length ratio, and wherein the quotient of said first width-to-length ratio divided by said second width-to-length ratio is a sense ratio;
• and
• a means to compare said first MOS transistor drain voltage and said second MOS transistor drain voltage wherein said first MOS transistor drain voltage exceeding said second MOS transistor drain voltage implies said load current value exceeds the product of said sense ratio multiplied by said constant current.

A current sense circuit comprising:

• a first NMOS transistor having a gate, a drain, and a source wherein said gate is coupled to a control signal, wherein said drain is coupled to a load such that a load current flows through said first NMOS transistor when said control signal is ON, and wherein said first NMOS transistor has a first width-to-length ratio;
• a second NMOS transistor having a gate, a drain, and a source wherein said gate is coupled to said control signal, wherein said drain is coupled to a constant current source such that said constant current flows through said second NMOS transistor when said control signal is ON, wherein:
• said source is coupled to said source of said first NMOS transistor, wherein said first and second MOS transistors are operating in the linear region when said control signal is ON, wherein said second NMOS transistor has a second width-to-length ratio, and wherein the quotient of said first width-to-length ratio divided by said second width-to-length ratio is a sense ratio;
• and
• a comparitor to compare said first NMOS transistor drain voltage and said second NMOS transistor drain voltage wherein said first NMOS transistor drain voltage exceeding said second NMOS transistor drain voltage implies said load current value exceeds the product of said sense ratio multiplied by said constant current.