Circuit pattern tape for wafer-scale production of chip size semiconductor packages

A chip size semiconductor package comprising:

• a semiconductor chip having edges and a plurality of die bonding pads on an active surface thereof;
• a circuit pattern tape laminated to said active surface of said chip, said circuit pattern tape having edges coincident with said edges of said chip, a central opening formed therein, a plurality of conductive metal bond fingers arranged around said opening, a plurality of conductive metal solder ball lands arranged around said bond fingers, a plurality of conductive metal traces electrically connecting respective ones of said bond fingers and said solder ball lands to each other, and an insulative solder mask formed over said circuit pattern tape and having a plurality of openings in it through which said central opening, said bond fingers, and said solder ball lands are respectively exposed;
• a plurality of solder balls, each attached to a respective one of said solder ball lands through a respective one of said openings in said solder mask and functioning as an input/output terminal of said package;
• a plurality of conductive bonding wires electrically connecting respective ones of said bond fingers on said tape and said die pads on said chip to each other through said central opening in said tape;
• and,
• a resin envelope encapsulating said central opening, said die pads, said bonding pads, and said bonding wires to protect them from harmful environmental elements, said envelope being formed thereon such that said envelope does not intersect any of said coincident edges of said tape and said chip.

A chip size semiconductor package comprising:

• a rectangular semiconductor chip having four exposed peripheral edges and a plurality of bonding pads on an active surface thereof;
• a rectangular circuit pattern tape laminated to said active surface of said chip, said circuit pattern tape having four outer edges each coincident with a corresponding peripheral edge of said semiconductor chip, and a rectangular central opening formed therein, wherein said central opening is entirely surrounded by intact portions of said circuit pattern tape;
• a plurality of circuit patterns having a first end adjacent said central opening and an opposite second end;
• a plurality of dummy circuit patterns on the circuit pattern tape, said dummy circuit patterns being electrically isolated;
• a plurality of conductive bonding wires, each extending between one of said bond pads and one of said first ends;
• and,
• a resin envelope encapsulating said central opening and covering a portion of the circuit tape around said opening, wherein said resin envelope does not extend to any of said four outer edges of the circuit tape.