Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry

A semiconductor wafer having void free dielectric filled high aspect ratio metal circuitry comprising:

• a) a silicon wafer having an upper lateral surface;
• b) a first titanium nitride layer covering the upper lateral surface of the silicon wafer;
• said first titanium nitride layer having a thickness of about 300 to 800 Angstroms;
• c) individual metal circuitry having spacing disposed on said first titanium layer;
• said metal circuitry having a thickness between 0.3 to 1.2 microns;
• said metal circuitry spacing having aspect ratios greater than 2, said metal circuitry being selected from a group consisting of aluminum, aluminum alloy, copper, copper, copper alloy, nickel and nickel alloys;
• d) a second titanium nitride later covering the upper surface of the metal circuitry said second titanium layer having a thickness of about 100 to 500 Angstroms;
• e) a void free first dielectric layer covering said individual metal circuitry lines and filling said spacing, said first dielectric layer having a thickness of about 5000 to 10000 Angstroms;
• said first dielectric layer conformal topography having an aspect ration of about 1.
• f) a void free second dielectric layer covering said first dielectric, said second dielectric layer having a thickness of about 3000 to 7000 Angstroms;
• said second dielectric layer having a planar upper surface.