Semiconductor device and manufacturing method thereof
AssigneeNEC Corporation
InventorShigeo Chishiki
Life of this patent
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Abstract
A semiconductor device and a semiconductor device manufacturing method provide a self align contact hole which is easy to restrain deterioration of insulation characteristics between an upper wiring layer connecting to a lower wiring layer via a self matching self align contact hole for a middle wiring layer and a middle wiring layer. The side of a bit contact hole which is self matching for a gate electrode is directly covered with a silicon oxide film spacer and a silicon oxide film spacer is reflowed and covered with a BPSG film spacer. With these processes, the restraint of the deterioration of insulation characteristics is implemented.
Claims5
A semiconductor device, comprising:
- a substrate, including first and second diffusion regions at first and second cross-sections, respectively;
- an insulation layer covering said first and second diffusion regions;
- a first conductor at said first cross-section formed on said insulation layer over said first diffusion region and connected to said first diffusion region through a first contact hole formed in said insulation layer;
- a second conductor at said second cross-section formed on said insulation layer over said second diffusion region and connected to said second diffusion region through a second contact hole formed in said insulation layer;
- and
- first and second film spacers of at least one of BPSG and PSG formed respectively in said first and second contact holes at said first and second cross-sections, respectively,
- wherein a concentration of impurity dopant of one of said first and second film spacers is lower than that of the other and
- wherein said first and second cross-sections are different from each other.
Dependencies are inferred from the claim text.