Memory cell having a deep trench capacitor and a vertical channel

A semiconductor memory cell, comprising:

• a substrate having a plurality of deep trenches arranged in array;
• a deep trench capacitor formed in each deep trench, wherein the deep trench capacitor comprises a storage node formed in the substrate and surrounding the deep trench, a capacitor dielectric formed on the sidewall of the deep trench, and an electrode plate filling the deep trench;
• an isolating layer covering the deep trench capacitor and having a first contact hole to expose a predetermined region of the electrode plate, wherein the exposed region of the electrode plate is a first doped region;
• a control gate electrode patterned on the isolating layer over the deep trench capacitor;
• a gate insulating layer covering the sidewall and top of the control gate electrode;
• and
• a well Si layer covering the exposed isolating layer and the exposed gate insulating layer, wherein one side of the well Si layer fills the first contact hole and the other side of the well Si layer is a second doped region.

A method of forming a semiconductor memory cell, comprising steps of:

• providing a substrate having a plurality of deep trenches arranged in array;
• forming a deep trench capacitor in each deep trench, wherein each deep trench capacitor comprises a storage node formed in the substrate and surrounding the deep trench, a capacitor dielectric formed on the sidewall of the deep trench, and an electrode plate filling the deep trench;
• forming an isolating layer to cover the deep trench capacitors;
• forming a control gate electrode over the deep trench capacitor;
• forming a gate insulating layer to cover the sidewall and top of the control gate electrode;
• forming a first contact hole in the gate insolating layer, wherein the first contact holes is at one side of the control gate electrode;
• forming a well Si layer to cover the isolating layer and the gate insulating layer and fill the first contact hole;
• forming a dielectric layer to cover the well Si layer, wherein the dielectric layer comprises a second contact hole to expose a predetermined region of the well Si layer that is at another side of the control gate electrode;
• and
• forming a second doped region on the exposed region of the well Si layer.

A method of forming a semiconductor memory cell, comprising steps of:

• providing a substrate having a plurality of deep trenches;
• forming a deep trench capacitor in each deep trench, wherein the deep trench capacitor comprises a storage node formed in the substrate and surrounding the deep trench, a capacitor dielectric formed on the sidewall of the deep trench, and an electrode plate filling the deep trench;
• forming an isolating layer to cover the deep trench capacitor;
• forming a control gate electrode on the isolating layer over the deep trench capacitor;
• forming a gate insulating layer to cover the sidewall and top of the control gate electrode;
• forming a first contact hole in the isolating layer to expose a predetermined region of the electrode plate, wherein the first contact hole is at one side of the control gate electrode;
• forming a first doped region on the exposed region of the electrode plate;
• forming a well Si layer to cover the isolating layer and the gate insulating layer and fill the first contact hole;
• forming a dielectric layer to cover the well Si layer, wherein the dielectric layer comprises a second contact hole to expose a predetermined region of the well Si layer that is at the other side of the control gate electrode;
• and
• forming a second doped region on the exposed region of the well Si layer.