Architectural structure of a process netlist design tool
AssigneeThe Boeing Company
InventorsMichael I Mandell, Arnold L. Berman
Life of this patent
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Abstract
A computer-implemented design tool architecture provides a mechanism for characterizing a circuit at a hardware level. The tool architecture has a medium for storing a description of an application specific integrated circuit (ASIC), where the description describes the ASIC at a behavioral level of a hierarchy. A library of foundry primitives map known ASIC components to code sets for a hardware description language (HDL). The tool architecture further includes a command interpreter for generating an electronic file based on a set of predefined computer-based commands such that the electronic file characterizes the circuit at the hardware level. The hardware level is at a lower level in the hierarchy than the behavioral level.
Claims20
A computer-implemented method for characterizing a circuit at a hardware level, the method comprising the steps of:
- receiving a description of the circuit, the description characterizing the circuit at a behavioral level of a hierarchy;
- interpreting a set of predefined computer-based commands requesting desired modifications in the description of the circuit;
- and
- generating an electronic file based on the computer-based commands such that the electronic file characterizes the circuit at a hardware level in a desired programming language, the hardware level being at a lower level in the hierarchy than the behavioral level.
A computer-implemented method for generating an electronic file, the method comprising the steps of:
- implementing desired modifications in a description of a circuit with a set of predefined modules based on computer-based commands and a library of foundry primitives, the foundry primitives mapping known components to code sets for a desired programming language;
- generating a hierarchical netlist representing the circuit at each level in a hierarchy;
- and
- repeatedly updating the hierarchical netlist in accordance with the modifications.
A computer-implemented design tool architecture comprising:
- a medium for storing a description of an application specific integrated circuit (ASIC), the description describing the ASIC at a behavioral level of a hierarchy;
- a library of foundry primitives, the foundry primitives mapping known ASIC components to code sets for a hardware description language;
- and
- a command interpreter for generating an electronic file based on a set of predefined computer-based commands such that the electronic file characterizes the circuit at a hardware level, the hardware level being at a lower level in the hierarchy than the behavioral level.
Dependencies are inferred from the claim text.