Method of embedding RAMS and other macrocells in the core of an integrated circuit chip

A method of embedding and optimizing placement of macrocells in an integrated circuit core, comprising:

• defining a first column and a second column, said first column having a first conducting rail on a first side of said first column that extends vertically from a first location in a conducting ring to a second location in said conducting ring and a second conducting rail on a second side of said first column that extends vertically from a third location in said conducting ring to a fourth location in said conducting ring, said second column having a third conducting rail on a first side of said second column that extends vertically from a fifth location in said conducting ring to a sixth location in said conducting ring and a fourth conducting rail on a second side of said second column that extends vertically from a seventh location in said conducting ring to an eighth location in said conducting ring;
• determining a first arrangement of macrocells and standard cells, said first arrangement having a plurality of macrocells in said defined first column and said defined second column with a first macrocell being placed in said defined first column, said first arrangement further having standard cells being placed inside or outside of a particular column and coupled to a conducting rail of said particular column;
• determining a second arrangement of said plurality of macrocells in said defined first column and said defined second column, wherein said second arrangement differs from said first arrangement by placement of said first macrocell in said defined second column rather than said defined first column, wherein said first macrocell has been moved from said defined first column to said defined second column;
• and
• embedding said defined first column and said defined second column in said core.