Automatic test pattern generation modeling for LSSD to interface with Muxscan

An apparatus for circuit modeling for use with an automatic test pattern generator of an L2 Star storage element and a Muxscan storage element comprising:

• a master latch that receives a master input signal upon assertion of a write clock signal;
• a slave latch that generates a slave output signal upon assertion of a master observe clock signal;
• a master observe control module that models an interface between the L2 Star storage element and the Muxscan storage element,
• wherein the master observe control module alternatively latches the master input signal from the master latch and the slave output signal from the slave latch upon assertion of a slave observe clock signal, and
• wherein the master observe control module is a flip-flop.

An apparatus for circuit modeling for use with an automatic test pattern generator of a level sensitive scan design storage element and a non-level sensitive scan design storage element comprising:

• means for modeling the level sensitive scan design storage element;
• means for modeling the non-level sensitive scan design storage element;
• and
• flip-flop means for modeling the interface between the level sensitive scan design storage element and the non-level sensitive scan design storage element.

A method of modeling a level sensitive scan design storage element and a non-level sensitive scan design storage element for testing with an automatic test pattern generator comprising:

• generating a slave output signal from a slave element;
• generating a master input signal for a master element;
• and
• alternatively selecting the slave output signal and the master input signal with a master observe control module, wherein the master observe control module is a flip-flop circuit.

A method of modeling an L2 Star storage element and a Muxscan design storage element for testing with an automatic test pattern generator comprising:

• receiving a master input signal for a master latch upon assertion of a write clock signal;
• generating a slave output signal from a slave latch upon assertion of a master observe control signal;
• alternatively latching the master input signal and the slave output signal with a master observe control module that models an interface between the L2 Star storage element and the Muxscan storage element,
• wherein the master observe control module alternatively latches the master input signal and the slave output signal upon assertion of a slave observe clock signal, and
• wherein the master observe control module is a flip-flop.