Technique for partitioning data to correct memory part failures

A system comprising:

• a processor;
• a bus;
• a memory system coupled to said processor and said bus, comprising:
• a plurality of first components is configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits, and wherein each bit of said data block is assigned to one of said plurality of first components;
• a plurality of second components configured to transfer bits of said data block, wherein each bit of said data block is assigned to one of said plurality of second components;
• and
• an error detection circuit coupled to said first components and said second components, wherein said error detection circuit is configured to:
• generate one or more check bits of a given one of said logical groups from data bits of the given one of said logical groups;
• verify the accuracy of the data bits of the given one of the said logical groups using the check bits of the given one of said logical groups;
• wherein said data bits and said check bits are grouped to form a plurality of logical groups, and wherein said logical group includes at most one bit assigned to a given one of said plurality of first components and at most one bit assigned to a given one of said plurality of second components;
• and
• wherein a number of said logical groups is selected to be greater than a number of bits of said data block stored in each of said plurality of first components.

A method of detecting errors in a data block of a computer system that includes a plurality of components, said method comprising:

• assigning a plurality of bits of said data block to a plurality of logical groups such that each of said logical groups includes at most one bit corresponding to a given one of said plurality components, wherein said plurality of bits of said data block includes a plurality of data bits and a plurality of check bits;
• and
• performing error correction on bits within each logical group of said plurality of logical groups, wherein said error correction is performed upon detection of at least one error in said bits,
• selecting number of bits in each of said logical groups to be less than a number of said components in said plurality components.

A method of detecting errors in a data block of a computer system that includes a plurality of first components and a plurality of second components wherein bits of said data block correspond to a first component and a second component, said method comprising:

• assigning said bits of said data block to a plurality of logical groups such that at most one bit corresponding to a given one of said plurality of first components is assigned to a first logical group of said plurality of logical groups and at most one bit corresponding to a given one of said plurality of second components is assigned to said first logical group;
• performing error detection on bits within said first logical group, wherein said first logical group includes a plurality of data bits and a plurality of check bits;
• and
• selecting a number of bits in said first logical group to be less than a number of said components in said plurality of first components.

An apparatus for detecting errors in a data block of a computer system including a plurality of components, said apparatus comprising:

• means for assigning a plurality of bits of said data block to a plurality of logical groups such that at most one bit of said plurality of bits corresponding to a given one of said components is assigned to any given one of said logical groups, wherein said plurality of bits of said data block includes a plurality of data bits and a plurality of check bits;
• and
• means for performing error correction on bits within each of said logical groups, wherein said error correction is performed upon detection of at least one error in said bits;
• wherein a number of bits in any given one of said logical group is selected to be less than a number of said components in said plurality of components.