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US 6,477,678 B1Granted
Method and device for error correcting coding for high rate digital data transmissions, and corresponding decoding method and device
AssigneeAlcatel
InventorsJuing Fang, Vincent Lemaire
Life of this patent
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Abstract
It is proposed to use channel coding involving a plurality of concatenated coders and decoders in series and in parallel for coded transmission in which the efficiency can be adapted as a function of the requirements of a system and an application. The coders of the invention are convolutional self-orthogonal code (CSOC) coders. It is shown that this enables perfect adaptation with circuits whose complexity and cost are low and which therefore support high bit rates.
Claims19
An error correcting coding method, comprising:
- coding streams of bits using a convolutional self-orthogonal coding circuit,
- converting the bits of said streams into sub-blocks,
- performing parallel orthogonal convolutional coding of the bits of the sub-blocks to produce sub-symbols in parallel, wherein the convolutional self-orthogonal codes have an efficiency of m/(m+1), where m represents the number of bits in a sub-block, and
- concatenating the sub-symbols,
- wherein the concatenating of the sub-symbols is followed by a step of orthogonal convolutional coding of the concatenated sub-symbols.
2 more elements
An error correcting coding method, comprising:
- coding streams of bits using a convolutional self-orthogonal coding circuit,
- converting the bits of said streams into sub-blocks,
- performing parallel orthogonal convolutional coding of the bits of the sub-blocks to produce sub-symbols in parallel, wherein the convolutional self-orthogonal codes have an efficiency of m/(m+1), where m represents the number of bits in a sub-block, and
- concatenating the sub-symbols,
- wherein the convolutional self-orthogonal codes are one or more of:
- the 8/9, 7, 3519 (R, J, NA) type,
- the 9/10, 7, 4860 (R, J, NA) type, and
- the 16/17, 6, 11594 (R, J, NA) type.
5 more elements
An error correcting coding method, comprising:
- coding streams of bits using a convolutional self-orthogonal coding circuit,
- converting the bits of said streams into sub-blocks,
- performing parallel orthogonal convolutional coding of the bits of the sub-blocks to produce sub-symbols in parallel, wherein the convolutional self-orthogonal codes have an efficiency of m/(m+1), where m represents the number of bits in a sub-block, and
- concatenating the sub-symbols,
- wherein the converting of the bits of the streams into sub-blocks is performed by a cascaded succession of CSOC coding and multiplexing interleaving.
2 more elements
An error correcting coding and decoding method, comprising:
- coding streams of bits using a convolutional self-orthogonal coding circuit,
- converting the bits of said streams into sub-blocks,
- performing parallel orthogonal convolutional coding of the bits of the sub-blocks to produce sub-symbols in parallel, wherein the convolutional self-orthogonal codes have an efficiency of m/(m+1), where m represents the number of bits in a sub-block, and
- concatenating the sub-symbols,
- decoding the convolutional self-orthogonal codes using majority logic decoders.
2 more elements
A coding apparatus, comprising:
- a mux/demux unit converting streams of bits, to be coded, into sub-blocks of bits,
- convolutional self-orthogonal coding (CSOC) circuits, in parallel, coding the bits of said sub-blocks and producing corresponding sub-symbols in parallel, and each having an efficiency of m/(m+1) where m represents the number of bits of a sub-block of bits, and
- a concatenation circuit for concatenating the sub-symbols,
- wherein:
- the mux/demux unit includes another CSOC coding circuit and an interleaver,
- the CSOC coding circuit of the mux/demux unit receives the streams of bits, and outputs coded streams of bits, and
- the interleaver provides the sub-blocks of bits from the coded streams of bits.
4 more elements
A coding apparatus, comprising:
- a mux/demux unit converting streams of bits, to be coded, into sub-blocks of bits (41-43),
- convolutional self-orthogonal coding (CSOC) circuits, in parallel, coding the bits of said sub-blocks and producing corresponding sub-symbols in parallel, and each having an efficiency of m/(m+1) where m represents the number of bits of a sub-block of bits,
- a concatenation circuit for concatenating the sub-symbols, and
- another CSOC circuit for coding the sub-symbols.
1 more element
Dependencies are inferred from the claim text.