Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips

An intermediate stage of a multi-stage algorithmic pattern generator, which is comprised of:

• a plurality of input address registers which hold respective input addresses;
• a plurality or input address generator, coupled to said input address registers, which generates a series of memory addresses by selecting bits from said input addresses;
• a memory, coupled to said memory address generator, which sequentially receives each memory address in said series, an in response, sends a corresponding series of translated addresses to a memory output;
• and,
• multiple output registers, coupled to said memory output, each of which stores a respective translated address in said series;
• wherein said memory address generator includes multiple multiplexers that each pass one bit of said input addresses for every memory address in said series;
• and, a control register that sequentially sends different sets of control signals to said multiplexers which select the particular bits to pass.

An intermediate stage of a multi-stage algorithmic pattern generator, which is comprised of:

• a plurality of input address registers which hold respective input addresses;
• a memory address generator, coupled to said input address registers, which generates a series of memory addresses by selecting bits from said input addresses;
• a memory, coupled to said memory address generator, which sequentially receives each memory address in said series, and in response, sends a corresponding series of translated addresses to a memory output;
• multiple output address registers, coupled to said memory output, each of which stores a respective translated address in said series;
• and,
• wherein said input address registers are partitioned into multiple subsets;
• and said memory stores different translated addresses for each subset.