Method and apparatus for generating expect data from a captured bit pattern, and memory device using same

A packetized dynamic random access memory, comprising:

• a clock generator circuit controlling the phase of an internal clock signal relative to an external clock signal responsive to a phase command signal;
• at least one array of memory cells adapted to store data at a location determined by a row address and a column address;
• a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals;
• a command buffer receiving command packets and initialization packets having a predetermined value, the command buffer including a latch storing each of the received packets responsive to a transition of the internal clock signal, the command buffer further generating a respective command words and initialization words corresponding to each received command packet and initialization packet, respectively;
• a pattern generator that generates expect data for a repeating bit sequence applied on external terminals of the packetized dynamic random access memory, comprising,
• a register having a plurality of inputs and outputs, and a clock terminal adapted to receive a clock signal, the register shifting data applied on each of its inputs to a corresponding output responsive to the clock signals,
• a switch circuit having a plurality of first signal terminals coupled to receive latched digital signals from the latch, a plurality of second signal terminals coupled to corresponding inputs of the register, and a control terminal adapted to receive a seed signal, the switch circuit coupling each first signal terminal to a corresponding second signal terminal responsive to the seed signal being active,
• a logic circuit coupled between the register inputs and outputs, and having a terminal adapted to receive the seed signal, the logic circuit generating, when the seed signal is inactive, new expect digital signals on the register inputs responsive to current expect digital signals provided on the register outputs;
• and
• a synchronization circuit coupled to the latch in the command buffer, clock generator, and pattern generator, the synchronization circuit, during a synchronization mode of the packetized dynamic random access memory, activating the seed signal to seed the pattern generator with a data pattern captured by the latch, and thereafter deactivating the seed signals, sequentially adjusting the phase command, and comparing the digital signals stored by the latch to expected values developed by the pattern generator, the synchronization circuit determining an optimum phase command from the results of the comparisons and applying that phase command to the clock generator during normal operation of the packetized memory device.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory, comprising,
• a clock generator circuit controlling the phase of an internal clock signal relative to an external clock signal responsive to a phase command signal;
• at least one array of memory cells adapted to store data at a location determined by a row address and a column address;
• a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address responsive to a first set of command signals;
• a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second set of command signals;
• a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third set of command signals;
• a command buffer receiving command packets and initialization packets having a predetermined value, the command buffer including a latch storing each of the received packets responsive to a transition of the internal clock signal, the command buffer further generating a respective command words and initialization words corresponding to each received command packet and initialization packet, respectively;
• a pattern generator that generates expect data for a repeating bit sequence applied on external terminals of the packetized dynamic random access memory, comprising,
• a register having a plurality of inputs and outputs, and a clock terminal adapted to receive a clock signal, the register shifting data applied on each of its inputs to a corresponding output responsive to the clock signals,
• a switch circuit having a plurality of first signal terminals coupled to receive latched digital signals from the latch, a plurality of second signal terminals coupled to corresponding inputs of the register, and a control terminal adapted to receive a seed signal, the switch circuit coupling each first signal terminal to a corresponding second signal terminal responsive to the seed signal being active,
• a logic circuit coupled between the register inputs and outputs, and having a terminal adapted to receive the seed signal, the logic circuit generating, when the seed signal is inactive, new expect digital signals on the register inputs responsive to current expect digital signals provided on the register outputs;
• and
• a synchronization circuit coupled to the latch in the command buffer, clock generator, and pattern generator, the synchronization circuit, during a synchronization mode of the packetized dynamic random access memory, activating the seed signal to seed the pattern generator with a data pattern captured by the latch, and thereafter deactivating the seed signals, sequentially adjusting the phase command, and comparing the digital signals stored by the latch to expected values developed by the pattern generator, the synchronization circuit determining an optimum phase command from the results of the comparisons and applying that phase command to the clock generator during normal operation of the packetized memory device.