Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

A method of conducting a loop back test in an integrated circuit comprising:

• generating a first test signal at a first pattern generator circuit in a first input/output (110) buffer;
• transmitting the first test signal from a first output driver in the first I/O buffer;
• receiving the first test signal at a first input receiver in the first I/O buffer;
• determining whether the first test signal received at the first input receiver is the equivalent to the first test signal as generated at the first pattern generator circuit;
• and
• if not, transmitting an error signal.

An input/output (I/O) buffer comprising:

• an I/O pad;
• an output driver coupled to the I/O pad;
• an input receiver coupled to the I/O pad;
• and
• an I/O test circuit, coupled to the output driver and the input receiver, that generates test pattern signals and test data signals corresponding to the test pattern signals whenever the integrated circuit is operating in a test mode.

A method of conducting a switching state (AC) loop back test at a buffer circuit comprising:

• varying the relationship between the generation of strobe signals at a strobe input/output (I/O) circuit of a first group of I/O circuits and the reception of data at the first group of I/O circuits until a first I/O circuit of the first group of I/O circuits receiving the strobe signals fail;
• comparing the time at which the first I/O circuit fails with predetermined timing performance for the first group of I/O circuits;
• and
• determining whether the first group of I/O circuits satisfies the predetermined timing performance.

A method of conducting a switching state (AC) loop back test at a buffer circuit comprising:

• varying the propagation of test data signals with respect to the reception of a common clock at a first group of input/output (I/O) circuits until a first I/O circuit of the first group fails;
• comparing the time at which the first I/O circuit fails with predetermined timing performance for the first group of I/O circuits;
• and
• determining whether the first group of I/O circuits satisfies the predetermined timing performance.