Structure and method with which to generate data background patterns for testing random-access-memories

Circuitry of a random access memory (RAM) that provides for programmability of data background patterns used to test the RAM, comprising:

• a shift register element that receives a programming information signal and a clock signal and shifts in and outputs the programming information signal in accordance with the clock signal;
• a logic element that receives the programming information signal from the shift register and a data bit of a data background pattern and performs an exclusive- or (XOR) function on the programming information signal and the data bit of the data background pattern to generate a programmed data bit;
• and
• a multiplexer element controlled by a test control signal that receives an application data bit and the programmed data bit, wherein when the test control signal is a first logic state indicative of a testing mode of the RAM the multiplexer element selects and outputs the programmed data bit to an input/output buffer of the RAM and when the test control signal is a second logic state indicative of a normal operating mode of the RAM the multiplexer element selects and outputs the application data bit to the input/output buffer of the RAM.

Circuitry of a random access memory (RAM) that provides for programmability of data background patterns used to test the RAM, comprising:

• a plurality of shift register elements, one for each data bit of a plurality of data bits of a data background pattern, that each receive a programming information signal and a clock signal and shift in and output the programming information signal in accordance with the clock signal to generate a plurality of clocked programming information signals;
• a plurality of logic elements, one for each data bit of the plurality of data bits of the data background pattern, that each receive a clocked programming information signal of the plurality of clocked programming information signals from a corresponding shift register element of the plurality of shift register elements, receive a corresponding data bit of the plurality of data bits of the data background pattern, and perform an exclusive-or (XOR) function on the clocked programming information signal and the corresponding data bit of the data background pattern to generate a plurality of programmed data bits;
• and
• a plurality of multiplexer elements, one for each data bit of the plurality of data bits of the data background pattern, that are each controlled by a test control signal and that each receive a corresponding application data bit of a plurality of application data bits of an application data and a programmed data bit of the plurality of programmed data bits, wherein when the test control signal is a first logic state indicative of a testing mode of the RAM the plurality of multiplexer elements select and output the plurality of programmed data bits to an input/output buffer of the RAM and when the test control signal is a second logic state indicative of a normal operating mode of the RAM the multiplexer elements select and output the plurality of application data bits of the application data to the input/output buffer of the RAM.

A method for programming data background patterns used to test the RAM, comprising the steps of:

• providing a data background pattern comprising a plurality of data bits to a RAM to be tested;
• providing a programming information signal to the RAM;
• selectively programming the plurality of data bits of the data background pattern in accordance with the programming information signal provided to the RAM to generate a programmed test data pattern;
• and
• providing the programmed test data pattern to one or more input/output buffers of the RAM when the RAM is in a testing mode as indicated by a test control signal.