US 6,477,671 B2 · Semiconductor memory, memory device, and memory card

Abstract

A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

Claims18

Dependent claims

A nonvolatile memory device comprising:

a plurality of nonvolatile memory cells;
a chip-selecting signal terminal;
and
a plurality of address terminals,
wherein said nonvolatile memory device is arranged to operate in a plurality of operation modes including a first operation mode and a second operation mode,
wherein, if said chip-selecting signal terminal receives a first status signal, said nonvolatile memory device is capable of accessing said nonvolatile memory cells, when said nonvolatile memory device is in said first operation mode, and
wherein, if said chip-selecting signal terminal receives a first status signal and a part of said address terminals receives a second status signal, said nonvolatile memory device is capable of accessing said nonvolatile memory cells, and, if said chip-selecting signal terminal receives said first status signal and said part of said address terminals receives a third status signal, said nonvolatile memory device is not capable of accessing said nonvolatile memory cells, when said nonvolatile memory device is in said second operation mode.

4 more elements

A nonvolatile memory apparatus comprising:

a first chip-selecting signal terminal;
a plurality of first address terminals;
and
a plurality of nonvolatile memory chips, each of which is integrated in one semiconductor substrate;
wherein each of said nonvolatile memory chips includes a second chip-selecting signal terminal and a plurality of second address terminals,
wherein said second chip-selecting signal terminal of a first nonvolatile memory chip and said second chip-selecting signal terminal of a second nonvolatile memory chip are coupled to said first chip-selecting signal terminal,
wherein said second address terminals of said first nonvolatile memory chip and said second address terminals of said second nonvolatile memory chip are coupled to said first address terminals bit by bit,
wherein, if a part of said first address terminals receives a first status signal, said part of said second address terminals of said first and said second nonvolatile memory chips also receive said first status signal, and said first nonvolatile memory chip is capable of accessing memory cells therein and said second nonvolatile memory chip is not capable of accessing memory cells therein, when said first chip-selecting signal terminal receives a predetermined status signal, and
wherein, if said part of said first address terminals receives a second status signal, said part of said second address terminals of said first and said second nonvolatile memory chips also receive said second status signal, and said first nonvolatile memory chip is not capable of accessing memory cells therein and said second nonvolatile memory chip is capable of accessing memory cells therein, when said first chip-selecting signal terminal receives said predetermined status signal.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory, memory device, and memory card

Life of this patent

Semiconductor memory, memory device, and memory card

Life of this patent

Abstract

Claims18