Signal generation circuit of semiconductor testing apparatus
AssigneeAndo Electric Co., Ltd.
InventorKiyoshi Ito
Life of this patent
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Abstract
A signal is generated according to the waveform information designated by a program and outputted by the format channels 1 and 2. Skew correction circuits 51 to 54 are provided corresponding to the format channel 1 and 2, and the signal outputted from the corresponding format channel is used as the reference, and the skew of the signal outputted from the other format channel is corrected. Logical add circuits 61 to 64 are provided corresponding to the skew correction circuits 51 to 54, and compose the signal from the corresponding skew correction circuit and the signal from the format channel to which this skew correction circuit corresponds.
Claims6
A signal generation circuit of a semiconductor testing apparatus comprising:
- a plurality of signal generation sections to generate a signal according to the waveform information designated by a program to output;
- a plurality of skew correction sections which are provided corresponding to said plurality of signal generation sections, and by using the signal outputted from corresponding signal generation section as the reference, correct the skew of the signal outputted from the other signal generation sections;
- and
- a plurality of signal composition sections which are provided corresponding to said plurality of skew correction sections, and compose the signal from said corresponding skew correction section and the signal from said signal generation section to which said skew correction section corresponds.
A signal generation circuit of a semiconductor testing apparatus comprising:
- a plurality of selection circuits to select one from a plurality of timing edges, and
- a correction circuit to correct the skew of the signal, inputted from a logical add circuit into a composition circuit, wherein
- the output of said selection circuit is connected to a formatter circuit,
- the output from said formatter circuit is connected to said logical add circuit,
- the output of said logical add circuit is connected to said composition circuit by which the output of said logical add circuit is composed with the same other outputs.
Dependencies are inferred from the claim text.