Breakpoint interrupt generating apparatus in a superscalar microprocessor

A breakpoint interrupt generation apparatus in an n-way superscalar microprocessor comprising:

• an address control means for inputting n addresses in parallel and then producing one by one the inputted address every cycle and outputting a stall signal and a complete signal, said stall signal indicating that an input operation for the next n addresses should be installed until all of the inputted addresses are outputted, and said complete signal indicating when all of the inputted addresses are outputted;
• a breakpoint address memory for storing at least one breakpoint address;
• an address match means for comparing the output of the address control means with the breakpoint address, so as to produce an address match signal;
• and
• a logic means for checking whether a breakpoint is generated every cycle based on the address match signal from the address match means and generating a breakpoint interrupt signal based on the address match signal when the complete signal is generated.

An address match circuit in a breakpoint interrupt generation apparatus of a superscalar microprocessor, for detecting whether an inputted address corresponds to a predetermined range of address requiring a breakpoint interrupt generation, comprising:

• a breakpoint address memory for storing a breakpoint address that is start address requiring a breakpoint interrupt generation;
• a range memory for storing the predetermined range of address;
• an operand size memory for storing a size value of an operand being performed;
• a subtractor for subtracting the inputted address from the breakpoint address;
• and
• a detecting means for detecting that the output of the subtractor is equal to or larger than an inverted value of the size value of the operand and that the output of the subtractor is equal to or less than the predetermined range of address.