Apparatus and method implementing repairs on a memory device

A method of testing a memory array having a plurality of memory cells organized into rows and columns, the memory array being connected to an address circuit for accessing the rows and columns and a test circuit for controlling the address circuit and for identifying a repair, said method comprising the steps of:

• a) providing a repair circuit coupled to the plurality of memory cells and the test circuit;
• b) writing via the test circuit test data into memory cells of the array to be tested;
• c) accessing via the address circuit a row of memory cells in the array;
• d) determining at the test circuit if any of the accessed memory cells are defective;
• e) if it is determined that any of the accessed memory cells are defective, incrementing a failure counter, comparing the failure counter to a first failure threshold, and if the failure counter exceeds the first failure threshold, repairing via the repair circuit the addressed cells prior to accessing additional memory cells of the array;
• and
• f) repeating steps d) through e) until all rows of the memory array have been tested.

A method of testing a memory array having a plurality of memory cells organized into rows and columns, the memory array being connected to an address circuit for accessing the rows and columns, said method comprising the steps of:

• a) providing a test circuit coupled to the plurality of memory cells and the address circuit for controlling the address circuit to access memory cells in a row or column direction and for identifying a repair when a predetermined number of defective memory cells in a same row or column are detected;
• b) providing a repair circuit coupled to the plurality of memory cells and the test circuit;
• c) writing via the test circuit test data into memory cells of the array to be tested;
• d) accessing via the address circuit a column of memory cells in the array;
• e) determining at the test circuit if any of the accessed memory cells are defective;
• f) if it is determined that any of the accessed memory cells are defective, incrementing a failure counter, comparing the failure counter to a first must-repair threshold and a first preferred-repair threshold, and if the failure counter exceeds one of the first must-repair threshold and the first preferred-repair threshold, repairing via the repair circuit the addressed cells prior to accessing additional memory cells of the array;
• g) repeating steps e) through f) until all columns of the memory array have been tested;
• h) accessing via the address circuit a row of memory cells in the array;
• i) determining at the test circuit if any of the accessed memory cells are defective;
• j) if any of the accessed memory cells are defective, incrementing the failure counter, comparing the failure counter to a second must-repair threshold and a second preferred-repair threshold, and if the failure counter exceeds the second must-repair threshold and the second preferred-repair threshold, repairing via the repair circuit the addressed cells prior to accessing additional memory cells of the array;
• and
• k) repeating steps h) through j) until all rows of the memory array have been tested.