Measuring timing margins in digital systems by varying a programmable clock skew

An apparatus that measures timing margins within a digital system by varying clock skew between components in the digital system, comprising:

• an input that receives a reference clock signal;
• a clock signal generation mechanism that is configured to generate a first clock signal and a second clock signal from the reference clock signal so that there exists a first clock skew between the first clock signal and the second clock signal;
• wherein the first clock signal is coupled to a first component in the digital system and the second clock signal is coupled to a second component in the digital system;
• a margin measuring mechanism that is configured to,
• iteratively increase the first clock skew and test the digital system until the digital system stops operating correctly, and
• set an upper margin to be an amount the first clock skew was increased before the digital system stopped operating correctly;
• wherein the margin measuring mechanism is further configured to:
• iteratively decrease the first clock skew and test the digital system until the digital system stops operating correctly;
• and
• set a lower margin to be an amount the first clock skew was decreased before the digital system stopped operating correctly;
• and
• a clock skew setting mechanism that is configured to:
• use the upper margin and the lower margin to compute an optimum clock skew value, and to
• set the first clock skew to the optimum clock skew value for subsequent operation of the digital system.

A computer system that measures timing margins within the computer system by varying clock skew between components that make up the computer system, comprising:

• a processor;
• a memory;
• an input that receives a reference clock signal for the computer system;
• a clock signal generation mechanism that is configured to generate a first clock signal and a second clock signal from the reference clock signal so that there exists a first clock skew between the first clock signal and the second clock signal;
• wherein the first clock signal is coupled to a first component in the computer system and the second clock signal is coupled to a second component in the computer system;
• a margin measuring mechanism that is configured to,
• iteratively increase the first clock skew and test the digital system until the digital system stops operating correctly, and
• set an upper margin to be an amount the first clock skew was increased before the computer system stopped operating correctly;
• wherein the margin measuring mechanism is further configured to:
• iteratively increase the first clock skew and test the digital system until the digital system stops operating correctly;
• and
• set a lower margin to be an amount the first clock skew was decreased before the computer system stopped operating correctly;
• and
• a clock skew setting mechanism that is configured to:
• use the upper margin and the lower margin to compute an optimum clock skew value, and to
• set the first clock skew to the substantially optimum clock skew value for operation of the digital system.

A computer readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for measuring timing margins within a digital system by varying clock skew between components in the digital system, comprising:

• receiving a reference clock signal;
• generating a first clock signal and a second clock signal from the reference clock signal so that there exists a first clock skew between the first clock signal and the second clock signal;
• sending the first clock signal to a first component in the digital system;
• sending the second clock signal to a second component in the digital system;
• determining an upper margin for the first clock skew by,
• iteratively increasing the first clock skew and testing the digital system until the digital system stops operating correctly, and
• setting the upper margin to be an amount the first clock skew was increased before the digital system stopped operating correctly;
• determining a lower margin for the first clock skew by:
• iteratively decreasing the first clock skew and testing the digital system until the digital system stops operating correctly, and
• setting the lower margin to be an amount the first clock skew was decreased before the digital system stopped operating correctly;
• using the upper margin and the lower margin to compute an optimum clock skew value;
• and
• setting the first clock skew to the optimum clock skew value for subsequent operation of the digital system.