Circuit for I/O clock generation

Abstract

Various apparatuses and methods to generate a clock signal that controls data operations in an integrated circuit. In an embodiment, a circuit for generating a clock signal that controls data operations in an integrated circuit includes a first clock synthesizer, a divider circuit, and a second clock synthesizer. The first clock synthesizer produces a first signal derived from an external reference signal. The first signal has a first frequency that is greater than a frequency of the external reference signal. The divider circuit divides the frequency of the first signal by N, where N is an integer greater than 1. The divider circuit outputs a second signal having a second frequency which is equal to the first frequency divided by N. The second clock synthesizer couples to the divider circuit for producing the clock signal at a frequency which is an integer multiple of the second signal. The second clock synthesizer also produces a strobe signal. The strobe signal has a rising edge that is either centered, or is coincident, with respect to a changing data signal of a processor.

Dependencies are inferred from the claim text.