Cryptographic checksum apparatus

A cryptographic checksum apparatus, comprising:

• a keystream generator for generating a secret keystream according to a common secret key;
• postfix means for augmenting a plurality of postfix bits after an original message, thereby generating a postfixed message;
• a demultiplexer having a plurality of output terminals, said demultiplexer being configured to direct the postfixed message to one of the output terminals under the control of the secret keystream;
• a plurality of mixers for individually receiving output of one output terminal of the demultiplexer;
• a plurality of compression circuits for individually receiving an output of the corresponding mixer, wherein content of each said compression circuit is used as a checksum output;
• a plurality of transmission gates for correspondingly receiving an output bit of the cross-feedback compression circuit, said output bit of the compression circuit being then transferred to the corresponding mixer through the corresponding transmission gate under control of the postfixed message.

A cryptographic checksum circuit, comprising:

• a keystream generator configured to generate a secret keystream according to a common secret key, said secret keystream including a string of binary random numbers;
• a postfix circuit configured to augment a plurality of postfix bits after an original message, thereby generating a postfixed message;
• a demultiplexer having two output terminals, said demultiplexer being configured to direct the postfixed message to one of the output terminals under the control of the secret keystream;
• a first logic exclusive OR gate configured to receive output of one output terminal of the demultiplexer;
• a second logic exclusive OR gate configured to receive output of the other output terminal of the demultiplexer;
• a first compression circuit configured to receive an output of said first logic exclusive OR gate, wherein content of said first compression circuit is used as a first part of a checksum output, said first compression circuit comprising a first shift register and a first digital switch connected therebetween, wherein an output of the first digital switch is fed to said first logic exclusive OR gate;
• a second compression circuit configured to receive an output of said second logic exclusive OR gate, wherein content of said second compression circuit is used as a second part of the checksum output, said second compression circuit comprising a second shift register and a second digital switch connected therebetween, wherein an output of the second digital switch is fed to said second logic exclusive OR gate;
• a first logic AND gate configured to receive an output bit of said second compression circuit and the postfixed message, output of said first logic AND gate being connected to said first logic exclusive OR gate;
• and
• a second logic AND gate configured to receive an output bit of said first compression circuit and the postfixed message, output of said second logic AND gate being connected to said second logic exclusive OR gate;
• thereby an attacker can only successfully forge the original message and the checksum with probability (1/4)t by changing last t bits of the postfixed message, the output of said first logic exclusive OR gate, and the output of said second logic exclusive OR gate.