Branch instruction mechanism for processor

A method of operating a processor using a branch control instruction, the method including the step of:

• (a) decoding a first portion of the branch control instruction, said first portion specifying target address information for a target address of an associated program branch instruction, said first portion including a variable amount of space as needed to define said target address information;
• and
• (b) decoding a second portion of the branch control instruction, said second portion identifying a target address register for storing said target address;
• and
• (c) decoding a third portion for specifying a prediction of whether said associated program branch instruction is likely to need a particular target instruction pointed to by said target address;
• (d) executing the branch control instruction before said associated program branch instruction in order to compute said target address before said associated program branch instruction is executed
• (e) controlling preloading of instructions in the processor based on said prediction, said preloading being associated with an operation to move instructions from a cache in the processor to an instruction buffer of the processor.

A branch control instruction for use by a processor, the branch control instruction being associated with a program branch and further being in an electronic form readable by the processor, the branch control instruction further having processor decodable portions including:

• (a) a first variable size portion in the branch control instruction allocated for specifying a target address for the program branch, said first portion including a variable amount of space as needed to define said target address;
• and
• (b) a second portion in the branch control instruction for specifying at least one of plurality of target address registers for storing said target address;
• and
• (c) a third portion in the branch control instruction for specifying a prediction of whether the program branch is likely to need a particular target instruction;
• wherein the branch control instruction is locatable in advance of a program branch instruction associated with the program branch so that the processor can compute said target address before said program branch instruction is executed.

A processor that executes a branch control instruction in conjunction with branch operations, the processor including:

• (a) a decoding unit, said decoding unit being adapted for:
• i) decoding a first portion of the branch control instruction, said first portion specifying target address information for a target address of an associated program branch instruction, said first portion including a variable amount of space as needed to define said target address information;
• and
• ii) decoding a second portion of the branch control instruction, said second portion identifying a target address register for storing said target address;
• and
• iii) decoding a third portion for specifying a prediction of whether said program branch is likely to need a particular target instruction pointed to by said target address;
• (b) an execution unit adapted for executing the branch control instruction before said associated program branch in order to compute said target address before said associated program branch instruction is executed;
• wherein a preloading operation is controlled based on said prediction, said preloading operation being associated with an operation to move instructions from a cache in the processor to an instruction buffer of the processor.