Synchronized instruction advancement through CPU and FPU pipelines

Abstract

A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU pipeline including a plurality of pipestages, wherein each CPU pipestage in the CPU pipeline has a corresponding pipestage in the FPU pipeline, a method of synchronizing operation of the CPU pipeline and the FPU pipeline, the method including the steps of (a) receiving an instruction in a first CPU pipestage, (b) receiving the instruction in a corresponding first FPU pipestage, (c) processing the instruction in the first CPU pipestage, (d) processing the instruction in the first FPU pipestage, (e) generating, by the first CPU pipestage, a first signal indicating that the instruction has been processed by first CPU pipestage and is ready to proceed to a second pipestage in the CPU pipeline, (f) generating by the first FPU pipestage, a second signal indicating that the instruction has been processed by the first FPU pipestage and is ready to proceed to a second pipestage in the FPU pipeline, (g) sending the instruction from the first CPU pipestage to the second pipestage in the CPU pipeline, (h) sending the instruction from the first FPU pipestage to the second pipestage in the FPU pipeline, (i) wherein the second pipestage in the CPU pipeline responds to the second signal to send the instruction to a third pipestage in the CPU pipeline, and (j) wherein the second pipestage in the FPU pipeline responds to the first signal to send the instruction to a third pipestage in the FPU pipeline. A corresponding apparatus is also provided.

Dependencies are inferred from the claim text.