Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing

A processor comprising

• a load/store unit having a level one (L1) cache and coupled to a memory subsystem, the load/store unit further having a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises:
• circuitry for receiving a snoop invalidate from the memory subsystem;
• circuitry for comparing a real address of the snoop invalidate to addresses in the real address tag array;
• circuitry for calculating an effective address corresponding to the real address of the snoop invalidates if the comparison results in a hit, and
• circuitry for using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array.

In a processor having a load/store unit coupled to an L1 cache and a level two (L2) cache, a method comprising the steps of

• receiving a real address within a real address tag array in the load/store unit, and
• correcting effective address aliasing within the load/store unit corresponding to the real address, wherein the correcting step further comprises the steps of
• receiving an L1 cache reload from the L2 cache,
• comparing a real address of the L1 cache reload to addresses in the real address tag array,
• calculating an effective address corresponding to the real address of the L1 cache reload if the comparison results in a hit,
• using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array, and
• reloading the L1 cache using the calculated effective address.

A data processing system comprising:

• a processor including a load/store unit;
• a primary cache,
• a secondary cache, and
• circuitry for coupling the processor to the primary cache and the secondary cache, wherein the load/store unit further comprises:
• a real address tag array for correcting effective address aliasing within the load/store unit, wherein the load/store unit further comprises:
• a latch receiving a primary cache reload from the secondary cache;
• a tag comparator comparing a real address of the primary cache reload to addresses in the real address tag array;
• circuitry for calculating an effective address corresponding to the real address of the primary cache reload if the comparison results in a hit;
• a clear tag port using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array;
• and
• circuitry for reloading the primary cache using the calculated effective address.

A data processing system comprising

• a processor including a load/store unit,
• a primary cache,
• a secondary cache, and
• circuitry for coupling the processor to the primary cache and the secondary cache, wherein the load/store unit further comprises
• a real address tag array for correcting effective address aliasing within the load/store unit wherein the load/store unit further comprises
• a latch receiving a snoop invalidate from the secondary cache,
• a tag comparator comparing a real address of the snoop invalidate to addresses in the real address tag array,
• circuitry for calculating an effective address corresponding to the real address of the snoop invalidate if the comparison results in a hit;
• and
• a clear tag port, coupling the real address tag array to an effective address tag array using the calculated effective address to clear the effective address tag array of any corresponding effective address in the effective address tag array.

In a processor having a load/store unit coupled to an L1 cache and an L2 cache, a method comprising the steps of:

• receiving a real address within a real address tag array in the load/store unit, and
• correcting effective address aliasing within the load/store unit corresponding to the real address, wherein the correcting step further comprises the steps of:
• receiving a snoop invalidate from the L2 cache;
• comparing a real address of the snoop invalidate to addresses in the real address tag array;
• calculating an effective address corresponding to the real address of the snoop invalidate if the comparison results in a hit;
• and
• using the calculated effective address to clear an effective address tag array of any corresponding effective address in the effective address tag array.