Memory device with pipelined address path
AssigneeMicron Technology, Inc.
InventorsChris G. Martin, Troy A. Manning
Life of this patent
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Abstract
In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array.
Claims5
A method of activating a row or column in each of a plurality of memory arrays in a packetized memory system, comprising the steps of:
- latching a first command packet;
- capturing a first set of addresses from the latched first command packet;
- latching the captured first set of addresses in response to a first timing signal;
- activating a first row or column of a first one of the memory arrays in response to the latched captured first set of addresses and a second timing signal;
- latching a second command packet;
- capturing a second set of addresses from the latched second command packet, the capturing of the second set of addresses starting during a first time interval for which the first row or column in the first one of the memory arrays is activated;
- latching the captured second set of addresses in response to a third timing signal;
- and
- activating a first row or column in a second one of the memory arrays in response to the latched captured second set of addresses and a fourth timing signal.
Dependencies are inferred from the claim text.