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US 6,477,630 B2Granted
Hierarchical row activation method for banking control in multi-bank DRAM
AssigneeInternational Business Machines Corporation
InventorsBrian Ji, Toshiaki Kirihata, Dmitry Netis
Life of this patent
Estimating the term…
Abstract
A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.
Claims12
A memory structure having hierarchical bank control, said memory structure comprising:
- a plurality of banks, wherein each one of said plurality of banks includes
- a plurality of word lines, wherein only one of said plurality of word lines within said each one of said plurality of banks can be activated at a time, and wherein
- each one of said plurality of banks is subdivided into a number of blocks within a bank, wherein each one of said blocks within a bank comprises a subset of said plurality of word lines;
- a plurality of bank timing lines wherein a respective one of said bank timing lines is coupled to a respective one of said plurality of banks in a one-to-one relationship;
- and
- a plurality of block lines, said plurality of block lines being equal in number to said number of said blocks within a bank, wherein each of said plurality of block lines is coupled to and shared with all of said plurality of banks, and
- wherein within each one of said plurality of banks,
- each of said blocks within a bank is coupled to and shared with said respective one of said bank timing lines, and a respective one of said plurality of block lines is coupled to said blocks within a bank in a one-to-one relationship with a respective one of said blocks within a bank.
5 more elements
A memory structure having hierarchical bank control, said memory structure comprising:
- a plurality of banks, wherein each one of said plurality of banks includes
- a plurality of word lines, wherein only one of said plurality of word lines within said each one of said plurality of banks can be activated at a time, and wherein
- each one of said plurality of banks is subdivided into a number of blocks within a bank wherein each one of said blocks within a bank further includes
- a signal generating device,
- a subset of said plurality of word lines, and
- at least one row decoder,
- wherein said at least one row decoder is coupled to said subset of word lines;
- a plurality of bank timing lines wherein a respective one of said bank timing lines is coupled to a respective one of said plurality of banks in a one-to-one relationship;
- and
- a plurality of block lines, said plurality of block lines being equal in number to said number of said blocks within a bank, wherein each of said plurality of block lines is coupled to and shared with all of said plurality of banks, and
- wherein within each one of said plurality of banks,
- each of said blocks within a bank is coupled to and shared with said respective one of said bank timing lines, and a respective one of said plurality of block lines is coupled to said blocks within a bank in a one-to-one relationship with a respective one of said blocks within a bank.
9 more elements
A memory structure having hierarchical bank control, said memory structure comprising:
- a plurality of banks, wherein each one of said plurality of banks includes
- a plurality of word lines, wherein only one of said plurality of word lines within said each one of said plurality of banks can be activated at a time, and wherein
- each one of said plurality of banks is subdivided into a number of blocks within a bank wherein each one of said blocks within a bank further includes
- a signal generating device,
- a subset of said plurality of word lines, and
- at least one row decoder,
- wherein said at least one row decoder is coupled to said subset of word lines;
- a plurality of bank timing lines wherein a respective one of said bank timing lines is coupled to a respective one of said plurality of banks in a one-to-one relationship;
- and
- a plurality of block lines, said plurality of block lines being equal in number to said number of said blocks within a bank, wherein each of said plurality of block lines is coupled to and shared with all of said plurality of banks, and
- wherein within each one of said plurality of banks,
- each of said blocks within a bank is coupled to and shared with said respective one of said bank timing lines, and a respective one of said plurality of block lines is coupled to said blocks within a bank in a one-to-one relationship with a respective one of said blocks within a bank, and
- wherein a selected word line address is hierarchically decoded by said signal generating device in cooperation with said at least one row decoder and a selected word line is activated in accordance with said selected word line address in a time period defined by information carried in said plurality of bank timing lines.
10 more elements
Dependencies are inferred from the claim text.