Simplified writeback handling

A processor system for improving writeback handling in a multi-processor computer system, at least one processor comprising:

• a main cache for storing data;
• a write cache for storing modified data;
• a writeback buffer for storing writeback data;
• and
• a merge unit having write ports coupled to respective read ports of the main cache and the write cache, and having a read port coupled to the writeback buffer and to the main cache, wherein during a writeback operation the merge unit merges data from the main cache with modified data from the write cache to generate the writeback data, and loads the writeback data into both the writeback buffer and the main cache.

A processor system for improving performance during a writeback operation in a multi-processor computer system, at least one processor comprising:

• a main cache having a read port and a write port, the main cache for storing frequently used data;
• a register file having a write port coupled to the read port of the main cache, and having a read port;
• a write cache having a write port coupled to the read port of the register file, and having a read port, the write cache for storing modified data;
• a merge unit having a first write port coupled to the read port of the main cache, a second write port coupled to the read port of the write cache, and a read port coupled to the write port of the main cache;
• and
• a writeback buffer having a write port coupled to the read port of the merge unit, the writeback buffer for storing writeback data.