US 6,477,620 B1 · Cache-level return data by-pass system for a hierarchical memory

Abstract

A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.

Claims20

Dependent claims

For use in a hierarchical memory including a main memory coupled to multiple cache memories, a memory by-pass system, comprising:

a first request processing circuit coupled to receive a request from the main memory, said request being initiated by any of the cache memories, said first request processing circuit to provide said request to an addressed one of the cache memories to cause said addressed one of the cache memories to return requested data signals to the main memory;
and
a first response generation circuit coupled to said first request processing circuit, to at least one associated one of the cache memories and to said addressed one of the cache memories, said first response generation circuit to receive from said addressed one of the cache memories said requested data signals, said first response generation circuit to generate a response including said requested data signals and that is to be provided directly to a cache memory that initiated said request if said cache memory that initiated said request is said at least one associated one of the cache memories.

For use within a hierarchical memory system including a main memory coupled to multiple first storage devices, and wherein each of the first storage devices is respectively coupled to respective other second storage devices, each of the first and second storage devices to store selected data signals retrieved from the main memory, predetermined ones of the multiple first storage devices each being coupled to at least one other associated one of the multiple first storage devices via a respective by-pass path, the method of managing the hierarchical memory system, comprising the steps of:

(a) providing a request from a requesting one of the first storage devices to the main memory, said request requesting a copy of addressed ones of the data signals stored in the main memory;
(b) generating a memory request from the main memory to a second one of the first storage devices to allow the main memory to retrieve the latest copy of said addressed ones of the data signals;
(c) retrieving said latest copy of said addressed ones of the data signals from said second one of the first storage devices to be provided to the main memory;
and
(d) routing said latest copy of said addressed ones of the data signals from said second one of the first storage devices directly to said requesting one of the first storage devices if said second one of the first storage devices and said requesting one of the first storage devices are coupled to each other via one of the respective by-pass paths.

2 more elements

A hierarchical memory system, comprising:

a main memory to store data signals;
multiple first memories coupled to said main memory each to initiate requests to said main memory to obtain a copy of requested ones of said data signals stored by said main memory, wherein ones of said requests are each routed by said main memory to a respectively selected one of said first memories to cause said selected one of said first memories to retrieve said requested ones of the data signals to be returned to said main memory to be further forwarded to the one of said first memories initiating said request;
and
a by-pass circuit coupled to at least two of said first memories to intercept said requested ones of said data signals retrieved from any of said at least two of said first memories and to provide intercepted ones of said data signals directly to a different one of said at least two of said first memories if said different one of said at least two of said first memories is the one of said first memories initiating the request associated with said requested ones of the data signals.

1 more element

Dependencies are inferred from the claim text.

Cache-level return data by-pass system for a hierarchical memory

Life of this patent

Cache-level return data by-pass system for a hierarchical memory

Life of this patent

Abstract

Claims20