US 6,477,609 B1Granted

Bridge state-machine progression for data transfers requested by a host bus and responded to by an external bus

AssigneeKoninklijke Philips Electronics N.V.

InventorsLoren B. Reiss, Bonnie C. Sexton, D. Adam Shiel

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Abstract

An expansion module for a Handspring Visor (which conforms to the Springboard bus specification) includes a multi-master AMBA Advanced System Bus (ASB). Optionally, an Arm7 processor is attached to this bus via an Arm7 to ASB interface as one master. The Springboard bus of the visor is coupled to the ASB bus via a Springboard-to-ASB-bus bridge. This bridge comprises a protocol translator and a second Arm7 to ASB interface. The protocol translator translates bi-directionally between the Springboard bus protocol and the Arm7TDMI protocol. The translator includes an interface to the Springboard bus and a state machine. The state machine coordinates data transfers between the buses. The state machine also monitors signals indicating when each of said buses begins to treat a data transfer as complete so that the data transfer can be validated or flagged as an error condition. A programmable counter adjusts maximum counts to compensate for different clock frequencies in measuring a write-wait state duration to ensure valid writes from the Visor to the ASB bus. Using this basic design framework, a developer of Springboard expansion modules can take immediate advantage of the performance and the variety of peripherals available for the ASB bus. Furthermore, using the same translator and merely changing the interface to the external bus, a Springboard developer can take advantage of peripherals developed for other external buses as well.

A bridge for managing data transfers that are requested by a host processor and directed via a host bus to an external bus, where said external bus can provide for wait states that are variable on a per-transfer basis, while said host bus utilizes wait states that are not variable on a per-transfer basis, said bridge comprising:

a host-bus interface to said host bus;
an external-bus interface to said external bus, said external-bus interface being coupled to said host-bus interface via data and address lines;
and
a state machine, said being coupled to said interfaces for receiving control signals therefrom and for providing said control signals thereto, said state machine receiving from said host-bus interface a “data-transfer” signal indicating when said host bus is treating a data transfer as active, said state machine receiving from said host-bus interface a “read/write” signal indicating whether a data-transfer request is for a read or a write operation, said state machine receiving from said external-bus interface a “wait” signal indicating when said external bus is treating a data transfer as active, said state machine providing to said external-bus interface a “request” signal when a data-transfer request is being made, said state machine providing to said host-bus interface a “valid” signal indicating when read data provided via said external-bus interface is valid, said state machine including the following states
an “idle” state in which said state machine is in only while said data-transfer signal is inactive, said state machine while in said idle state holding said request signal inactive and said valid signal inactive,
an “access-wait” state in which said state machine is in only while said data-transfer signal is active and while said wait signal is active, said state machine while in said access-wait state holding said valid signal inactive, said state machine moving, directly or indirectly, from said idle state to said access wait state only when said data-transfer signal becomes active, and
an “access-hold” state in which said state machine is in only while said data-transfer signal is active and while said wait signal is inactive, said state machine moving from said access-wait state to said access-hold state only when said wait signal goes inactive while said data-transfer signal is active, said state-machine in said access-hold state holding said valid signal active, said state machine moving from said access-hold state to said idle state only when said data-transfer signal becomes inactive.

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Abstract

Claims10