US 6,477,608 B1 · Interface circuit for transferring data on bus between modules of integrated circuit with reduced delay

Abstract

As the signal lines, such as the data bus, become longer, signal delay occurs due to the resistance and capacitance components of that bus. In order to minimize the effect due to this delay, the processing module is designed in consideration of the delay time. An interface circuit 13 is provided in the bus to control the signal transfer. Data and so forth sent from the central processing unit is supplied directly to the extended bus without being delayed in the interface circuit. Data signals and so forth transferred to the central processing unit 11 is delayed for a predetermined time in the latch 25 of the interface circuit before being sent to the central processing unit. Because only the data signal to be sent to the central processing unit is latched, the size of the interface circuit can be minimized.

Claims15

Dependent claims

An interface circuit located between signal lines formed within an electronic device, said interface circuit comprising:

a first driver circuit for receiving first data information transferred from a central processing unit onto a data bus and for sending said first data information to said data bus on an extended bus side without delaying it;
a control circuit for receiving a control signal from a control line among said signal lines and for generating a data latch signal to control the transfer of second data information over said data bus on the extended bus side;
and
a data latch circuit for storing said second data information in response to said data latch signal and for sending said second data information to said data bus on a main side after a first predetermined time has passed.

1 more element

An integrated circuit formed on a semiconductor substrate, comprising:

a first plurality of module circuits for executing specific processes, respectively, said first plurality of module circuits including a central processing unit;
first signal lines coupled to said first plurality of module circuits, respectively, for transmitting address information, data information, and control signals;
a second plurality of module circuits for executing specific processes, respectively;
second signal lines coupled to said second plurality of module circuits, respectively, for transmitting said address information, said data information, and said control signals;
and
an interface circuit located between said first signal lines and said second signal lines for sending and receiving said address information, said data information, and said control signals therebetween, said interface circuit sending without delay said data information on said first signal lines to said second signal lines and storing said data information on said second signal lines and then sending said data information to said first lines after a predetermined time has passed.

3 more elements

Dependencies are inferred from the claim text.

Interface circuit for transferring data on bus between modules of integrated circuit with reduced delay

Life of this patent

Interface circuit for transferring data on bus between modules of integrated circuit with reduced delay

Life of this patent

Abstract

Claims15