Duplexing structure of switching system processor and method thereof
AssigneeLC Information & Communications, Ltd.
InventorSang-Ik Jeong
Life of this patent
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Abstract
A duplexing structure of a switching system processor in which a duplexing channel is formed through a back plane to implement duplexing in an active mode and a standby mode includes first and a second processor boards for which a duplexing channel is formed through a back plane and being dually operated in an active mode and in a standby mode, wherein each processor bus connected to a microprocessor of a processor board at one side, and a duplexing channel connected to a processor board at the other use a different clock so that the two processor boards are independently operated.
Claims19
A switching system processor, comprising:
- a first processor board coupled to a first microprocessor and a first memory via a first bus;
- a second processor board coupled to a second microprocessor and a second memory via a second bus;
- and
- a duplex channel device coupled to the first bus and the second bus, that accesses a duplex channel, such that data is transferred between at least one of the first microprocessor and the second microprocessor, and at least one of the first memory and the second memory,
- wherein the first microprocessor and the second microprocessor operate at a first clock and the duplex channel is operated at a second clock, which is different from the first clock.
A duplex channel device that accesses a duplex channel to transfer data to a first peripheral device via a first bus and a second peripheral device via a second bus, comprising:
- a first storage device coupled to a first processor board and the first bus, that temporarily stores the data;
- a second storage device coupled to a second processor board and the second bus, that temporarily stores the data;
- a first duplex channel controller coupled to the first storage device and a duplex channel, that arbitrates the use of the duplex channel and controls the transferring of the data between the first storage device and the second storage device;
- and
- a second duplex channel controller coupled to the second storage device and the duplex channel, that arbitrates the use of the duplex channel with the first duplex channel controller and controls the transferring of the data between the second storage device and the first storage device, wherein the first duplex channel controller and the second duplex channel controller operate the duplex channel at a frequency independent of the first and second peripheral devices.
A method of duplexing a switching system processor including a first processor board coupled to a first microprocessor and a first memory via a first bus, and a second processor board coupled to a second microprocessor and a second memory via a second bus, comprising:
- (a) transferring data, including an address signal and a data signal, to and from at least one of the first and second microprocessors at a first clock;
- and
- (b) transferring the data between the at least one of the first and second microprocessors and at least one of the first and second memories, via first and second duplex channel controllers coupled to a duplex channel, at a second clock, which is different from the first clock.
Dependencies are inferred from the claim text.