SCSI bus free phase management structure and method of operation for parallel SCSI host adapter integrated circuits

Abstract

A parallel SCSI host adapter integrated circuit includes a Bus Free management circuit having a plurality of input lines coupled to SCSI bus control terminals of said parallel SCSI host adapter integrated circuit; a Bus Free phase interrupt disable line; a clear line; a Bus Free phase status line; and a Bus Free phase interrupt line. The Bus Free management circuit automatically generates an active signal on said Bus Free phase status line following receipt of (i) one of a selection complete signal and a reselection complete signal on said plurality of input lines; and (ii) a Bus Free phase signal on said plurality of input lines. The parallel SCSI host adapter integrated circuit also includes a sequencer coupled to said clear line, to said Bus Free phase status line, and to said Bus Free phase interrupt disable line. The sequencer generates an active signal on said Bus Free phase interrupt disable line when a Bus Free phase is expected. The sequencer also generates an active signal on said clear line after determining that an active signal is on said Bus Free phase status line.

Dependencies are inferred from the claim text.