Apparatus and method for processing isochronous interrupts
AssigneeIntel Corporation
InventorsBrent S. Baxter, John I. Garney
Life of this patent
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Abstract
A computer system provides for the use of isochronous interrupts by devices coupled with the system. Isochronous interrupt requests are received by an interrupt controller during a first time period, recorded, and executed during a second time period. The devices are equipped to handle the delay in interrupt execution. The interrupt controller is set to service isochronous interrupts on a periodic basis. The interrupt controller may flexibly schedule the execution of the isochronous interrupt request at any time during the second time period.
Claims31
A method for processing interrupts, comprising:
- receiving a first interrupt during a first time period;
- delaying the execution of a first interrupt handling routine corresponding to the first interrupt until a second time period;
- and
- executing the first interrupt handling routine before the end of the second time period.
A method for processing interrupts, comprising:
- receiving a number of interrupt requests during a first time period of duration T, each of the number of interrupt requests originating at a device;
- determining, for each of the number of interrupt requests, whether the interrupt requests that is isochronous, recording the receipt of the interrupt request during the first time period;
- scheduling the generation of at least one microprocessor interrupt signal during a second time period of duration T corresponding to a respective one of the number of interrupt requests that is isochronous;
- generating the at least one microprocessor interrupt signal during the second time period;
- receiving the at least one microprocessor interrupt signal in a microprocessor;
- and
- executing a respective interrupt handling routine corresponding to the at least one microprocessor interrupt signal before the end of the second time period.
An interrupt handling system, comprising:
- an input port;
- an output port;
- and
- an interrupt controller coupled to the input port and the output port, the interrupt controller including an isochronous interrupt controller to process at least one isochronous interrupt request received via the input port during a first time period and generate an interrupt signal at the output port during a second time period to execute the interrupt signal before the end of the second time period.
A computer system, comprising:
- a microprocessor having an interrupt processing facility;
- an interrupt controller coupled to the microprocessor to provide the microprocessor with a microprocessor interrupt signal, the interrupt controller including an isochronous interrupt controller to receive an interrupt request during a first time period, and to schedule execution of an interrupt handling routine corresponding to the interrupt request by the microprocessor before the end of a second time period.
Dependencies are inferred from the claim text.