Bus controlling method and apparatus for delaying activation of a bus cycle
AssigneeSanyo Electric Co., Ltd.
InventorsHiroki Miura, Yasuhito Koumura, Kenshi Matsumoto
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Abstract
With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output disable times of external devices such as a first device are utilized. When a device with a long output disable time is read in a bus cycle, an idle state is forcibly inserted before a following bus cycle activation to avoid a data conflict.
Claims7
A bus cycle controlling method which, when write or read access is made following a previous access of a first device in a current bus cycle in a successive access operation for a second device, considers an output disable time of the first device being accessed in the current bus cycle, to delay activation of a following bus cycle for the following write or read access, when such delay is necessary to avoid data conflicts between data of the previous access and read or write data of the following read or write access caused by a long output disable time, the delay in activating the following bus cycle being accomplished by inserting a preset number of necessary idle state according to the output disable time of said first device, and to prohibit insertion of said number of necessary idle state when no data conflict occurs, wherein the bus cycle controlling method does not insert an idle state during successive accesses when the first and second devices are the same single device.
A bus controlling equipment, comprising:
- a setting unit for setting a number of necessary idle state of a device to be accessed;
- and
- a controlling unit for inserting the number of necessary idle state after a current bus cycle, in response to an output disable time of a first device being accessed in the current bus cycle,
- wherein controlling unit inserts the number of necessary idle state if the first device accessed in the current bus cycle requires a delay to prevent conflict with access to a second device in a bus cycle following the current bus cycle and does not insert an idle state if the first device accessed in the current bus cycle will not conflict with an access to the second device in the bus cycle following the current bus cycle or if the first and second device are the same single device.
Dependencies are inferred from the claim text.