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US 6,477,557 B1Granted
Division circuit not requiring taking complements of divisor, dividend and remainder
AssigneeKabushiki Kaisha Toshiba
InventorNaoka Yano
Life of this patent
Estimating the term…
Abstract
In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if small, the quotient of that column is regarded as 0 upon this division.
Claims14
A division circuit comprising:
- a comparator configured to compare the sign of a dividend and the sign of a divisor;
- an adder/subtractor configured to carry out addition or subtraction for data of predetermined bits of partial dividend to be input and the divisor according to comparison result of the comparator and output result of the addition or subtraction as data of predetermined bits of a temporary partial remainder, the data of the predetermined bits of the partial dividend at a first cycle being data obtained by adding predetermined extension bits including a sign bit to a high-order side of the dividend, the data of the predetermined bits of the partial reminder at the following cycles being data obtained by logically shifting a partial reminder of a preceding cycle to the left by one bit;
- an all zero detector configured to determine whether or not the temporary partial remainder is 0, the temporary partial remainder being obtained by connecting the data of the predetermined bits of the temporary partial remainder and data of the partial dividend excluding the predetermined bits thereof;
- and
- a controller configured to determine one digit of a quotient based on the sign of the temporary partial remainder, the sign of the dividend and determination result of the all zero detector, select the data of the predetermined bits of the partial dividend or data of predetermined bits of the temporary partial remainder according to a value of the one digit of the quotient, connect the selected data with the data of the partial dividend excluding the predetermined bits thereof to obtain the partial remainder, then obtain the partial dividend for the next cycle from the partial remainder, further input the data of the predetermined bits of the partial dividend into the adder/subtractor, and thus control the adder/subtractor to repeat the addition or subtraction by a predetermined frequency.
2 more elements
A division circuit comprising:
- a comparator configured to compare the sign of a dividend and the sign of a divisor;
- an adder/subtractor configured to carry out addition or subtraction for data of predetermined bits of partial dividend to be input and the divisor and output result of the addition or subtraction as data of predetermined bits of a temporary partial remainder, the data of the predetermined bits of the partial dividend at a first cycle being data obtained by adding predetermined extension bits including a sign bit to a high-order side of the dividend, the data of the predetermined bits of the partial remainder at the following cycles being data obtained by logically shifting a partial reminder of a preceding cycle to the left by one bit;
- an all zero detector configured to determine whether or not the temporary partial remainder is 0, the temporary partial remainder being obtained by connecting the data of the predetermined bits of the temporary partial remainder and data of the partial dividend excluding the predetermined bits thereof;
- and
- a controller configured to determine one digit of a quotient based on the sign of the temporary partial remainder, the sign of the dividend and determination result of the all zero detector, instruct the adder/subtractor to carry out addition or subtraction of a next cycle, in a first cycle according to comparison result of the comparator and in the following cycles according to a value of the one digit of the quotient and the comparison result of the comparator, obtain the partial dividend for the next cycle from the temporal partial remainder, further input the data of the predetermined bits of the partial dividend into the adder/subtractor, and thus control the adder/subtractor to repeat the addition or subtraction by a predetermined frequency according to the value of the one digit of the quotient and the comparison result of the comparator.
2 more elements
Dependencies are inferred from the claim text.