System and method for fast parallel cone-beam reconstruction using one or more microprocessors
AssigneeUniversity of Rochester
InventorRuola Ning
Life of this patent
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Abstract
Cone-beam reconstruction is performed within a practically acceptable time on a computer having one or more microprocessors. The calculations involved in the reconstruction are divided into calculations to be performed on the MMX, ALU and SSE units of each of the microprocessors. For pure floating-point data, it is preferred to use the MMX unit to adjust the data address and map data and to use the SSE unit to perform the backprojection. The data are partitioned by z-line so that the data to be processed in each stage of the backprojection fit within the L1 cache.
Claims33
A system for generating a three-dimensional image representative of an interior portion of an object, the system comprising:
- a radiation scanner which generates projection signals by passing a radiation through the object onto a detector;
- and
- a computer, receiving the projection signals, for generating the three-dimensional image by performing a plurality of calculations on the projection signals, the computer comprising at least one fixed-point processing unit and at least one floating-point processing unit, the at least one fixed-point processing unit operating in parallel with the at least one floating-point processing unit, the computer dividing the plurality of calculations into a first plurality of calculations to be performed in the at least one fixed-point processing unit and a second plurality of calculations to be performed in the at least one floating-point processing unit.
A method of generating a three-dimensional image representative of an interior portion of an object, the method comprising:
- (a) passing a through the object onto a detector to generate projection signals;
- and
- (b) receiving the projection signals and generating the three-dimensional image by performing a plurality of calculations on the projection signals;
- wherein step (b) is performed on a computer comprising at least one fixed-point processing unit and at least one floating-point processing unit, the at least one fixed-point processing unit operating in parallel with the at least one floating-point processing unit, the computer dividing the plurality of calculations into a first plurality of calculations to be performed in the at least one fixed-point processing unit and a second plurality of calculations to be performed in the at least one floating-point processing unit.
Dependencies are inferred from the claim text.