Video image decoding method and apparatus
AssigneeKabushiki Kaisha Toshiba
InventorsMichihiro Fukushima, Shuji Abe, Masahiro Yamada
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AssigneeKabushiki Kaisha Toshiba
InventorsMichihiro Fukushima, Shuji Abe, Masahiro Yamada
Estimating the term…
When stream video image signal are decoded simultaneously, and synchronized so as to be displayed on a screen, it prevents the disturbance of the displayed video image caused by changing the master. The DEMUX 101 separates the each channel video image signal and PCR from the multiplexed stream. The separated video image signal is stored in the input buffer memories 107 through 101. The master selector comprised of the PCR selector 120 and the STC selector 121 select the master. The selected master STC, the comparator 123, the OPF 124 and the VCO125 comprise the PLL. From the VOC 125 the system clock is regenerated, and the synchronizing signal generator 126 generates the decode starting signal and the display synchronizing signal based on the system clock. From the STC counters 103 through 106 the reference time information of each channels are obtained. The decoding controllers 111 through 114 work over the each decoders 115 through 118 to start decoding based on the decode starting signal.
A decoding method for decoding a video image signal, comprising:
A decoder for decoding a video image signal comprising:
A decode processor configured to decode a stream of MPEG-encoded video image data transmitted in conjunction with reference time information, comprising:
A decode processor configured to decode n (n denotes an integer of 2 or more;
A decode processor configured to decode n (n denotes an integer of 2 or more;
A decode processor configured to decode n (n denotes an integer of 2 or more;
A decode processor configured to decode n (n denotes an integer of 2 or more;
A decode processor configured to decode n (n denotes an integer of 2 or more;
A decoded processor, which decodes n (n denotes an integer of 2 or more;
Dependencies are inferred from the claim text.