Signal processing distributed arithmetic architecture

A method for computing an inner product vector of a matrix and a vector, the matrix having a first set of coefficients arraigned in a set of rows and a set of columns, the vector having a second set of coefficients, comprising the steps of:

• generating a set of register outputs from the second coefficients of the vector;
• storing a set of pre-calculated partial sums derived from the first coefficients in a plurality of storage elements;
• selecting a matrix row to be multiplied with the vector to form a portion of the inner product vector;
• selecting a subset of pre-calculated partial sums from said stored set of pre-calculated partial sums based on said set of register outputs into said plurality of storage elements;
• adding said subset of pre-calculated partial sums in said adder circuit to create said portion of the inner product;
• and
• repeating the steps of selecting a matrix row, selecting a subset of pre-calculated partial sums, and adding said subset or pre-calculated partial sums for each row of the matrix.

A digital camera, comprising:

• a lens;
• an image sensor, said image sensor having an image capture area optically coupled to said lens, and said image sensor having a data output;
• an image processing integrated circuit, said image processing integrated circuit coupled to said data output of said image sensor, said image processing integrated circuit further comprising,
• a circuit for computing a set of inner product results of a matrix and a vector, the matrix having a first set of coefficients arranged in a set of rows and a set of columns, the vector having a second set of coefficients derived from said image sensor, and further comprising,
• a plurality of input registers, said plurality of input registers storing the second set of coefficients, said plurality of input registers having a set of outputs,
• a plurality of storage elements, said storage elements storing a set of partial sums derived from the first set of coefficients, said plurality of storage elements having a set of address inputs and a set of data outputs, said set of address inputs coupled to said set of outputs of said plurality of input registers, said plurality of storage elements having a set of data outputs for presenting a subset of said set of partial sums, said subset of said set of partial sums selected by said set of address inputs,
• a storage bank select circuit, said storage bank select circuit coupled to said set of address inputs of said plurality of storage elements, said storage bank select circuit selecting a row in the matrix to compute one inner product result from the selected row and the vector,
• a clock circuit, said clock circuit coupled to said plurality of input registers and said storage bank select circuit, said clock circuit creating a set of clock cycles corresponding to the number of rows of the matrix, and
• an adder circuit, said adder circuit having a summation output and a plurality of addend inputs, said plurality of addend inputs coupled to said set of data outputs of said storage elements, wherein each data output of said plurality of storage elements is coupled to one addend input to form one addend of the summation output, said summation output presents one inner product result of the set of inner product results corresponding to a row of the matrix multiplied by the vector for each clock cycle of said set of clock cycles;
• a camera controller, said camera controller coupled to said summation output of said image processing integrated circuit, said camera controller creating an image processed data output;
• and
• a image storage device, said image storage device coupled to said camera controller, said image storage device storing the image processed data output from said camera controller.