Fast operating multiplexer
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToru Nakura, Kimio Ueda
Life of this patent
Estimating the term…
Abstract
In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.
Claims10
A multiplexer for converting parallel data signals of M bits (M being an integer larger than 1) into a serial data signal of M bits in synchronization with a clock signal, comprising:
- a signal generating circuit for generating control signals of M phases each having a period M times larger than that of said clock signal, and being shifted in phase from each other by (1/M) of said period;
- a first holding circuit for temporarily holding said control signals of M phases issued from said signal generating circuit, and issuing said control signals in synchronization with said clock signal;
- a select circuit for successively selecting said parallel data signals of M bits bit by bit in response to the control signals of M phases issued from said first holding circuit, and producing said M-bit serial data signal by passing each of the selected data signals;
- and
- a second holding circuit for temporarily holding each of the data signals issued from said select circuit, and thereafter issuing said data signal in synchronization with said clock signal.
A multiplexer for converting parallel data signals of (M×N) bits (M and N being integers larger than one) into a serial data signal of (M×N) bits in synchronization with a clock signal, comprising:
- a first signal converting circuit for converting said parallel data signals of (M×N) bits into first to Mth parallel data signal columns each including a serial data signal of N bits;
- and
- a second signal converting circuit for converting said first to Mth parallel data signal columns into said serial data signal of (M×N) bits,
- said second signal converting circuit including:
- a first signal generating circuit for producing first control signals of M phases each having a period M times larger than that of said clock signal, and being shifted in phase from each other by (1/M) of said period,
- a first holding circuit for temporarily holding said first control signals of M phases issued from said first signal generating circuit, and thereafter issuing said first control signals in synchronization with said clock signal,
- a first select circuit for successively selecting one bit in each of said first to Mth parallel data signal columns in response to the first control signals of M phases issued from said first holding circuit, and producing said serial data signal of (M×N) bits by passing each of the selected data signals, and
- a second holding circuit for temporarily holding each of the data signals issued from said first select circuit, and thereafter issuing said data signal in synchronization with said clock signal.
Dependencies are inferred from the claim text.