Method and apparatus for interfacing between systems operating under different clock regimes with interlocking to prevent overwriting of data
AssigneeAdvanced Micro Devices, Inc.
InventorsJing Lu, Ching Yu
Life of this patent
Estimating the term…
Abstract
A method and apparatus for interfacing a central processing unit to a network switch with an external memory that transfers data to the network switch at a different clock speed than transfers of data to the central processing unit provides an interlocking mechanism to prevent overwriting of data and underflows from occurring. The interlocking of the state machines, accomplished by the idling and advancing of a processor state machine and an external memory state machine, prevents either one of the separate state machines from outrunning the other state machine.
Claims21
An interface for transferring information between a first system operating within a first clock regime and a second system operating within a second clock regime different from the first clock regime, the interface comprising:
- a first pipeline section connected to the first system;
- a second pipeline section connected to the second system;
- a first system state machine operating in accordance with the first clock regime to transfer information between the first system and the second pipeline section through the first pipeline section;
- a second system state machine operating in accordance with the second clock regime to transfer information between the second system and the first pipeline section through the second pipeline section;
- wherein the first system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the second system prior to continuing operation, and the second system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the first system prior to continuing operation.
A network switch for a packet switched network, comprising:
- a processor interface configured for connecting between a processor and a memory, the processor interface including:
- a first pipeline section connecting the processor interface to a processor;
- a second pipeline section connected to the first pipeline section and connecting the processor interface to a memory, the first and second pipeline sections operable at different respective clock speeds to respectively transfer data to and from a processor and to and from a memory;
- a first state machine that controls the filling and emptying of the first pipeline section;
- a second state machine that controls the filling and emptying of the second pipeline section;
- wherein the first and second state machines are interlocked such that transfers of data between the first and second pipeline sections is initiated only when the receiving one of the first and second pipeline sections is empty.
Dependencies are inferred from the claim text.