US 6,477,125 B1Granted

Decoding apparatus

AssigneeVictor Company of Japan, Ltd.

InventorAtsushi Hayami

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Abstract

An waveform equalizer equalizes the signal reproduced from an optical disc to remove reproduction waveform distortion with a frequency characteristic controlled. A binary coder and a PLL circuit generate a bit clock. An a/d converter a/d-converts the equalized signal in response to the bit clock. A Viterbi decoder including metric operation decodes the output of the a/d converter in response to the bit clock to output a bit stream. The metric operation generates a metric operation result from an output of the a/d-converter and prediction data. The Viterbi decoder Viterbi-decodes the output of the a/d converter through the metric operation according to prediction data. An operating circuit operates an equalizing error from the output of a/d converter and a waveform equalizing target. A coefficient generator controls the frequency characteristic according to the equalizing error to minimize the equalizing error. The prediction data for the metric operation is operated from the output of the a/d converter for better decoding. Instead the binary coder, data estimation and generating the bit clock signal is provided with a data estimation and PLL circuit. The bit clock signal is supplied to the Viterbi decoder and the estimated data is supplied to the Viterbi decoder and the operation circuit.

Claims2

Dependent claims

A decoding apparatus for decoding a signal reproduced from an optical disc comprising:

automatic gain control means for controlling an envelope level of a waveform of said signal to a predetermined level;
waveform equalizing means having a frequency characteristic for waveform-equalizing said signal from said automatic gain control means to remove reproduction waveform distortion of said signal, said frequency characteristic being changed in accordance with at least a tap coefficient;
binary coding means for binary-coding an output of the waveform equalizing means;
a phase-locked-loop circuit for generating a bit synchronizing clock signal on the basis of an output of said binary coding means;
a/d converting means for a/d-converting an output of said waveform equalizing means in response to said bit synchronizing clock signal;
Viterbi decoding means including metric operation means for Viterbi-decoding said output of the a/d converting means in response to said bit synchronizing clock signal to output a bit stream, said metric operation means generating a metric operation result from an output of the a/d-converting means and prediction data, said Viterbi decoding means Viterbi-decoding said output of said a/d converting means with said metric operation result;
error operating means for outputting an equalizing error from the output of said a/d converting means and waveform equalizing target data;
coefficient generation means for generating said tap coefficient from said equalizing error to minimize the equalizing error;
and
data predicting means for generating said prediction data in accordance with said output of said a/d converting means.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/438,297Filed 12 Nov 1999
Priority: JP 10-3618994 Dec 1998
Granted: 5 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11B 20/10296
Using probabilistic methods, e.g. maximum likelihood detectors: using the Viterbi algorithm
G11B 20/10092
Using partial response filtering when writing the signal to the medium or reading it therefrom: partial response PR
G11B 20/1024
Clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation: wherein a phase-locked loop [PLL] is used
G11B 20/10509
Optimisation methods: iterative methods, e.g. trial-and-error, interval search, gradient descent or feedback loops