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US 6,477,115 B1Granted
Semiconductor integrated circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsChizuru Inoshita, Kazuo Aoki
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit, a monitor circuit for evaluation is provided on a semiconductor substrate in an input/output buffer circuit region. This monitor circuit includes a delay circuit, a first flip-flop circuit on the input side of the delay circuit, and a second flip-flop circuit on the output side of the delay circuit.
Claims19
A semiconductor integrated circuit comprising:
- a semiconductor substrate on which various components can be mounted;
- an input/output buffer circuit region on said semiconductor substrate;
- and
- a monitor circuit to be evaluated and located in said input/output buffer circuit region, wherein said monitor circuit comprises a delay circuit, a first flip-flop circuit located at an input side of said delay circuit, and a second flip-flop circuit located at an output side of said delay circuit.
1 more element
A semiconductor integrated circuit comprising:
- a semiconductor substrate on which various components can be mounted;
- an input/output buffer circuit region on said semiconductor substrate;
- at least one built-in logic circuit;
- and
- a monitor circuit to be evaluated and located in said input/output buffer circuit region, wherein said monitor circuit comprises at least one delay circuit, a first flip-flop circuit located at an input side of said delay circuit, and a second flip-flop circuit located at an output side of said delay circuit.
2 more elements
Dependencies are inferred from the claim text.