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US 6,477,109 B2Granted
Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKiyohiro Furutani, Yasuhiro Konishi
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Abstract
In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.
Claims3
A semiconductor device comprising:
- a bit line pair;
- a word line;
- a memory cell coupled to said bit line pair and said word line;
- a sense amplifier for amplifying data on said bit line pair in response to a first signal activated in accordance with an active command;
- and
- a control circuit for resetting the first signal in response to an inactivation of a second signal which is activated for a period of time according to a burst length and a passage of a predetermined period of time after the first signal is activated.
3 more elements
Dependencies are inferred from the claim text.