Back to results
US 6,477,108 B2Granted
Semiconductor device including memory with reduced current consumption
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazutami Arimoto, Hiroki Shimano
Life of this patent
Estimating the term…
Abstract
When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.
Claims9
A semiconductor device comprising:
- a memory array including a plurality of memory cells arranged in rows and columns, for conducting data transmission and reception in response to an address signal in synchronization with an internal clock signal;
- and
- a clock processing circuit for transmitting a basic clock signal as said internal clock signal to said memory array in response to a command,
- said command including a row activation command that indicates start of a row selection operation of said plurality of memory cells for data transmission and reception to and from said memory array, and
- said clock processing circuit including
- an internal clock control circuit for activating an internal clock enable signal in response to said row activation command, and
- an internal clock generation circuit for outputting said internal clock signal based on said basic clock signal in response to activation of said internal clock enable signal, and deactivating said internal clock signal in response to deactivation of said internal clock enable signal wherein said internal clock control circuit includes
- an internal circuit for activating an internal control signal in response to said row activation command and a received clock enable signal, and
- a selection circuit for selecting said clock enable signal in a first mode and selecting said internal control signal in a second mode so as to output the selected signal as said internal clock enable signal.
6 more elements
A semiconductor device comprising:
- a memory array including a plurality of memory cells arranged in rows and columns, for conducting data transmission and reception in response to an address signal in synchronization with an internal clock signal;
- and
- a clock processing circuit for transmitting a basic clock signal as said internal clock signal to said memory array in response to a command,
- said command including a row activation command that indicates start of a row selection operation of said plurality of memory cells for data transmission and reception to and from said memory array, and
- said clock processing circuit including
- an internal clock control circuit for activating an internal clock enable signal in response to said row activation command, and
- an internal clock generation circuit for outputting said internal clock signal based on said basic clock signal in response to activation of said internal clock enable signal, and deactivating said internal clock signal in response to deactivation of said internal clock enable signal wherein said internal clock generation circuit includes
- a holding circuit for accepting said internal clock enable signal in response to said basic clock signal, and
- a gate circuit for outputting said basic clock signal as said internal clock signal in response to an output of said holding circuit.
6 more elements
A semiconductor device comprising:
- a memory array including a plurality of memory cells arranged in rows and columns, for conducting data transmission and reception in response to an address signal in synchronization with an internal clock signal;
- and
- a clock processing circuit for transmitting a basic clock signal as said internal clock signal to said memory array in response to a command,
- said command including a row activation command that indicates start of a row selection operation of said plurality of memory cells for data transmission and reception to and from said memory array, and
- said clock processing circuit including
- an internal clock control circuit for activating an internal clock enable signal in response to said row activation command, and
- an internal clock generation circuit for outputting said internal clock signal based on said basic clock signal in response to activation of said internal clock enable signal, and deactivating said internal clock signal in response to deactivation of said internal clock enable signal wherein said internal clock generation circuit includes
- a holding circuit for accepting said internal clock enable signal in response to said basic clock signal, and
- a gate circuit for immediately outputting said basic clock signal as said internal clock signal when said internal clock enable signal is activated, and outputting said basic clock signal as said internal clock signal in response to an output of said holding circuit when said internal clock enable signal is deactivated.
6 more elements
Dependencies are inferred from the claim text.