Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual data rate mode operation and methods of operating same

A semiconductor memory device operating in synchronicity with an external system clock, comprising:

• first and second memory arrays which include a plurality of memory cells, respectively;
• first and second data lines electrically coupled to the first and second memory arrays, respectively;
• a multiplexer which receives data on the first and second data lines, outputs data on the first data line in response to a first control signal and outputs data on the second data line in response to a second control signal;
• an internal clock generator which receives the external system clock and outputs a first internal clock;
• a divider which receives the first internal clock, divides the frequency of the first internal clock and outputs a second internal clock;
• and
• a control signal generator which generates the first and the second control signals from the first internal clock or the second internal clock in response to a mode control signal.

A semiconductor memory device operating in synchronicity with an external system clock, comprising:

• first and second memory arrays which include a plurality of memory cells, respectively;
• first and second data lines electrically coupled to the first and second memory arrays, respectively;
• a multiplexer which receives data on the first and second data lines, outputs data on the first data line in response to a first control signal and outputs data on the second data line in response to a second control signal;
• an internal clock generator which receives the external system clock and outputs a DDR (Double Data Rate) mode signal;
• a divider which receives the DDR mode signal, divides the frequency of the DDR mode signal and outputs a SDR (Single Data Rate) mode signal;
• and
• a control signal generator which generates the first and the second control signals from the DDR mode signal and the SDR mode signal in response to the state of a mode register.

A semiconductor memory device operating in synchronicity with an external system clock, comprising:

• a first memory array which writes to or reads data from a plurality of memory cells through first data lines;
• a second memory array which writes to or reads data from a plurality of memory cells through second data lines;
• a first IO sense amplifier which amplifies data on the first data lines and outputs the amplified data in response to a first control signal;
• a second IO sense amplifier which amplifies data on the second data lines and outputs the amplified data in response to the first control signal;
• a first data line selector which selects either the output of the first IO sense amplifier or the output of the second IO sense amplifier in response to a selection control signal, and outputs the selected data on a first data bus in response to a second control signal;
• a second data line selector which selects either the output of the first IO sense amplifier or the output of the second IO sense amplifier in response to a complimentary selection control signal, and outputs the selected data on a second data bus in response to a third control signal;
• a multiplexer which receives date on the first and second data lines, outputs data on the first data line in response to a fourth control signal and outputs data on the second data line in response to a fifth control signal;
• an internal clock generator which receives the external system clock and outputs a DDR (Double Data rate) mode signal;
• a divider which receives the DDR mode signal, divides the frequency of the DDR mode signal and outputs a SDR (Single Data Rate) mode signal;
• and
• a control signal generator which generates the first through fifth control signals from the DDR mode signal and the SDR mode signal in response to the state of a mode register.

An integrated circuit memory device, comprising;

• first and second memory arrays;
• first and second local data lines electrically coupled to the first and second memory arrays, respectively;
• a multiplexer having first and second inputs electrically coupled to first and second data lines, respectively;
• and
• a data selection circuit which routes data from the first and second local data lines to first and second data bus lines, respectively, when a selection control signal is in a first logic state, and routes data from the second and first local data lines to the first and second data bus lines, respectively, when the selection control signal is in a second logic state opposite to the first logic state.

An integrated circuit memory device, comprising:

• first and second memory arrays;
• first and second local data lines electrically coupled to the first and second memory arrays, respectively;
• a control signal generator which is responsive to an external clock signal, generates an internal clock signal having a period equal to nT or T/n, where n is an integer and T is the period of the external clock signal, and generates first through fifth control signals which are each synchronized with either a rising or falling edge of the internal clock signal;
• a multiplexer responsive to the fourth and fifth control signals and having first and second inputs electrically coupled to first and second data lines, respectively;
• and
• a data selection circuit which is responsive to the first through third control signals and a selection control signal, and routes data from the first and second local data lines to first and second data bus lines, respectively, when a selection control signal is in a first logic state, and routes data from the second and first local data lines to the first and second data bus lines, respectively, when the selection control signal is in a second logic state opposite to the first logic state.