Circuit configuration for deactivating word lines in a memory matrix

A circuit configuration for deactivating word lines in a memory matrix of a memory, comprising:

• a common supply line system carrying a deactivation potential for the word lines;
• controllable connection devices connected to said common supply line and to be connected to the word lines, said controllable connecting devices connecting each of the word lines to said common supply line system carrying the deactivation potential for the word lines;
• and
• a control circuit having an output connected to said controllable connection devices, said control circuit receiving a deactivation command and in response to the deactivation command produces a deactivation control signal available at said output, the deactivation control signal turns on said controllable connection devices resulting in turned-on controllable connection devices, said control circuit having a reduction device connected to said output and said reduction device can be switched on selectively and which, when switched on, limits currents flowing through said turned-on controllable connection devices to such an extent that a total current flowing through said common supply line system does not exceed a prescribed value.